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IDT5V9882T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

Integrated Device Technology 

IDT5V9882T

3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR

INDUSTRIAL TEMPERATURE RANGE

The spread spectrum parameters such as the modulation frequency and profile will not be enabled nor will it have any impact on the PLL output when the

PLL is programmed for fractional divide.

The following is an example of how to set the fractional divider.

Example

FIN = 20MHz, FOUT1 = 168.75MHz, FOUT2 = 350MHz

Solving for 350MHz using Eq.2 and Eq.3 with PLL0 and spread spectrum off,

350MHz = 20MHz * (M / D)

P*2

For better jitter performance, keep D as small as possible

350MHz * 2 = M = 35

20MHz P 1

Therefore, we have D = 1, M = 35 (N = 16, A = 2) for PLL0 with P = 1 on output bank4 resulting in 350MHz.

Solving for 168.75MHz with PLL1 and fractional divide enabled:

168.75MHz = 20MHz * (M / D)

P*2

168.75MHz * 2 = M = 16.875 or 33.75

20MHz P 1

2

The 33.75 value is chosen to achieve the highest VCO frequency possible. Next step is to figure out the setting for the fractional divide using Eq.3.

33.75 = 2*N + A + 1 + SS_OFFSET * 1/64

Integer value 33 can be determined by N and A, thus leaving 0.75 left to be solved.

2*N + A + 1 = 33

SS_OFFSET = 64 * 0.75 = 48

Therefore, we have D=1, M=33.75 (N=15, A=2, SS_OFFSET=48) for PLL1 with P=2 on an output bank resulting in 168.75MHz.

The fractional divider can be determined if it is needed by following the steps in the previous example. Note that the 5v9882T should not be programmed

with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to prevent an unstable state in the modulator. The A[3:0] must be used and set to be greater than

'2' for a more accurate fractional divide.

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