IDT49C465G Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza

componentes Descripción

Fabricante

IDT49C465G

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

Integrated Device Technology 

IDT49C465/A

32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTIONS (Con’t.)

Symbol I/O

Name and Function

Inputs (Con’t.)

MODE 2-0 I

CLEAR

I

SYNCLK

I

SCLKEN I

(x11)

(x10)

(000)

(x01)

(100)

MODE select: Selects one of four operating modes.

“Normal” Mode: Normal EDC operation (Flow-thru correction and generation).

“Generate-Detect” Mode: In this mode, error correction is disabled. Error generation and detection are

normal.

“Error-Data-Output” Mode: Allows the uncorrected data captured from an error event by the Error-Data

Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by toggling

CLEAR low. The Syndrome Register and Error-Data Register record the syndrome and uncorrected data

from the first error that occurs after they are reset by the CLEAR pin. The Syndrome Register and Error-Data

Register are updated when there is a positive edge on SYNCLK, an error condition is indicated (ERR = low),

and the Error Counter indicates zero.

All-Zero-Data Source: In Error-Data-Output Mode, clearing the Error-Data Register provides a source of

all-zero-data for hardware initialization of memory, if this desired.

Diagnostic-Output Mode: In this mode, the contents of the Syndrome Register , Error Counter and Error-

Type Register are output on the SD bus. This allows the syndrome bytes for an indicated error to be read

by the system for error-logging purposes. The Syndrome Register and the Error-Data Register are updated

when there is a positive edge on SYNCLK, an error condition is indicated and the Error Counter indicates

zero errors. Thus, the Syndrome Register saves the syndrome that was present when the first error occurred

after the Error Counter was cleared. The Syndrome Register and the Error Counter are cleared by toggling

CLEAR low. The Error Counter lets the system tell if more than one error has occurred since the last time

the Syndrome Register or Error-Data Register was read.

Checkbit-Injection Mode: In the “Checkbit-Injection” Mode, diagnostic checkbits may be input on System

Data Bus bits 0-7 (see Diagnostic Features - Detailed Description).

CLEAR: When the CLEAR pin is taken low, the Error-Data Register, the Syndrome Register, the Error

Counter and the Error-Type Register are cleared.

SYNdrome CLocK: If ERR is low, and the Error Counter indicates zero errors, syndrome bits are clocked

into the Syndrome Register and data from the outputs of the Memory Data input latch are clocked into the

Error-Data Register on the low-to-high edge of SYNCLK. If ERR is low, the Error Counter will increment on

the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen errors.

SynCLK ENable: The SCLKEN enables the SYNCLK signal. SYNCLK is ignored if SCLKEN is high.

Outputs and Enables

CBO0-7

O

CBOE

I

SYO0-7

O

ERR

O

MERR

O

PERR

O

Power Supply Pins

Vcc 1- 10

P

GND1-12

P

CheckBits-Out (00, 01)

Partial-CheckBits-Out (10)

Checkbits-Out (11):

In a single EDC system, the checkbits are output to the checkbit memory on these outputs. In the lower slice

in a cascaded EDC system, the “Partial-checkbits” used by the upper slice are output by these outputs

(Generate path only). In the upper slice in a cascade, the “Final-Checkbits” appear at these outputs

(Generate path only).

CheckBits Out Enable: Enables CheckBit Output drivers when low.

SYndrome-Out (00)

Partial-SYndrome-Out (10)

Partial-Checkbits-Out (11):

In a 32-bit EDC system, the syndrome bits are output on these pins. In the lower slice in a 64-bit cascaded

system, the “Partial-Syndrome” bits appear at these outputs (Detect/ Correct path). In the upper slice in a

cascaded EDC system, the “Partial-Checkbits” appear at these outputs (Correct path only). In a 64-bit

cascaded system, the “Final-Syndrome” may be accessed in the “Diagnostic-Output” Mode from either the

lower or the upper slice since the final syndrome is contained in both.

ERROR: When in “Normal” and “Detect only” modes, a low on this pin indicates that one or more errors have

been detected. ERR is not gated or latched internally.

Multiple ERRor: When in “Normal” and “Detect only” modes, a low on this pin indicates that two or more

errors have been detected. MERR is not gated or latched internally.

Parity ERRor: A low on this pin indicates a parity error which has resulted from the active bytes defined by

the 4 Byte Enable pins. Parity ERRor (PERR) is not gated or latched internally (see Byte Enable definition).

+5 Volts

Ground

2552 tbl 02

11.7

8

Share Link: