IDT49C465AG Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT49C465AG Datasheet PDF : 38 Pages
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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 64-BIT CONFIGURATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
64-BIT
to
U/L Slice
1
2
3
4
5
Parameter
Name
Propagation Delay
From
To
MOE
t MEMxZ
MD 0–31 (OUTPUT)
Valid DATAIN
t MMLS
t MMLH
CBI
Valid Checkbits In
t CMLS
t CMLH
MLE
PCBI
(1)
t MLS
Partial checkbits in from Upper
t MEMxZ MOE = High to MDOUT Disabled
t MMLS
t MMLH
MDIN Set-up to MLE = Low
MDIN Hold to MLE = Low
t CMLS
t CMLH
CBI Set-up to MLE = Low
CBI Hold to MLE = Low
t MLS(1) MLEIN = High to SDOUT (1)
Min./
Max.
max.
min.
min.
min.
min.
max.
PLE
BEN
SOE
SD0–31
P0–3
t PLS(1)
t BESZx
t SESZx
t CS
t CSY
t MS
t CSY
t MSY
t MP
t MLP
t PLP
t BEPZx
t SEP
t PLS(1)
(1)
PLE = Low to SDOUT
max.
t BESZx BEN = High to SDOUT Enabled
max.
t SESZx SOE = Low to SDOUT Enabled
max.
t CS
CBI to Corrected SDOUT
max.
t CSY
CBI to Syndrome
max.
t MS
MDIN to Corrected SDOUT
max.
Corrected DATAOUT
t CSY
CBI to Syndrome
max.
t MSY
MDIN to Syndrome
max.
t MP
MDIN to Parity Out
max.
t MLP
MLE = High to Parity Out
max.
t PLP
PLE = Low to Parity Out
max.
t BEPZx BEN = High to Parity Out
max.
t SEP
SOE = Low to Parity Out
max.
Parity Out
SYO
Partial Syndrome Out
to
1
2
3
4
5
NOTE:
1. Assumes that Memory Data and Checkbits are valid at least 4ns (Com.) before MLE goes HIGH.
Figure 12. 64-Bit Correct Timing (Lower Slice)
2552 drw 24
11.7
33
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