IDT49C465AG Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT49C465AG Datasheet PDF : 38 Pages
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IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
AC TIMING DIAGRAMS — 64-BIT CONFIGURATION
MILITARY AND COMMERCIAL TEMPERATURE RANGES
BOTH
to
465s
1
2
3
4
5
Parameter
Name
Propagation Delay
From
To
Min./
Max.
MOE
t MEMxZ
MD (L) (OUTPUT)
Valid DATAIN
t MMLS
t MMLH
CBI
Valid Checkbits In
t CMLS
t CMLH
MLE
BEN
SOE
t MLS(1)
t BESZx
t SESZx
t MEMxZ MOE = High to MDOUT
max.
Disabled
t MMLS MDIN Set-up to MLE = Low
min.
t MMLH MDIN Hold to MLE = Low
min.
t CMLS CBI Set-up to MLE = Low
min.
t CMLH CBI Hold to MLE = Low
min.
t MLS(1) MLE = High to SDOUT(1)
max.
t BESZx BEN = High to SDOUT Enabled
max.
t SESZx SOE = Low to SDOUT Enabled
max.
LOWER 465
SD0–31
SYO
UPPER 465
CBI
MERR
ERR
MD (U) (OUTPUT)
t MSY
t CSY
t MLSY
Corrected DATAOUT
Partial Syndrome Out
3
Partial Syndrome In
t CME
t MLME (1)
t CE
t MLE(1)
t ME
t MME
Valid DATAIN
t MSY
t CSY
t MLSY
MD Lower In to SYOOUT
CBI to SYO
MLE = High to SYO
Inter-chip delay (Design dependent)
t CME
CBI to MERR
t MLME(1) MLE = High to MERR
t CE
t MLE(1)
CBI to ERR
MLE = High to ERR
t ME
t MME
MDIN to ERR
MDIN to MERR
to
1
2
3
4
5
NOTE:
1. Assumes that System Data is valid at least 3ns (Com.)/4ns (Mil.) before SLE goes HIGH.
Figure 11. 64-Bit Detect Timing
max.
max.
max.
max.
max.
max.
max.
max.
max.
2552 drw 23
11.7
32
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