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ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS854057

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER

WITH INTERNAL INPUT TERMINATION

PARAMETER MEASUREMENT INFORMATION

V

DD

2.5V±5%

POWER SUPPLY

+ Float GND -

LVDS

V

DD

nPCLK0:

nPCLK3

Qx SCOPE

V

PP

PCLK0:

PCLK3

nQx

GND

Cross Points

V

CMR

2.5V OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

nPCLKx

PCLKx

nPCLKy

PCLKy

nQ

Q

INPUT SKEW

tPD2

tPD1

tsk(i)

tsk(i) = |tPD1 - tPD2|

nPCLK0:

nPCLK3

PCLK0:

PCLK3

nQ

Q

tPD

nQ

PART 1

Q

nQ

PART 2

Q

t sk(pp)

PART-TO-PART SKEW

nQ

Q

t PW

t

PERIOD

odc = t PW x 100%

t PERIOD

PROPAGATION DELAY

854057AG

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

www.icst.com/products/hiperclocks.html

6

REV. A JULY 18, 2005

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