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ICS85401AKT

2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS85401

2:1

DIFFERENTIAL-TO-LVDS MULTIPLEXER

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1

CLK0

Input Pulldown Non-inverting differential clock input.

2

nCLK0

Input

Pullup/

Pulldown

Inverting differential clock input. VDD/2 default when left floating.

3

CLK1

Input Pulldown Non-inverting differential clock input.

4

nCLK1

Input

Pullup/

Pulldown

Inverting differential clock input. VDD/2 default when left floating.

5, 7, 16

nc

Unused

Unused pins.

Clock select input. When HIGH, selects CLK1, nCLK1 inputs.

6

CLK_SEL Input Pulldown When LOW, selects CLK0, nCLK0 inputs.

LVCMOS / LVTTL interface levels.

8, 13

9, 12, 14, 15

VDD

GND

Power

Power

Positive supply pins.

Power supply ground.

10, 11

nQ, Q

Output

Differential output pair. LVDS interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

CIN

RPULLUP

RPULLDOWN

Parameter

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Test Conditions

Minimum

Typical

1

37

37

Maximum

Units

pF

kΩ

kΩ

TABLE 3. CONTROL INPUT FUNCTION TABLE

Input

CLK_SEL

0

1

Clock Out

CLK

CLK0, nCLK0

CLK1, nCLK1

85401AK

www.icst.com/products/hiperclocks.html

2

REV. A FEBRUARY 22, 2005

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