ICS527-02
Clock Slicer User Configurable PECL Input Zero Delay Buffer
Parameter
Input Capacitance
Short Circuit Current
On-chip pull-up resistor
Symbol Conditions
CIN Except PECLIN and
FBIN
IOS
RPU
Min.
Typ.
5
Max.
Units
pF
±70
mA
270
kΩ
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
FIN
1.5
Output Frequency, CLK1
FOUT 0 to +70°C
2.5
-40 to +85°C
4
Output Rise Time
tOR 0.8 to 2.0 V, CL=15 pF
1
Output Fall Time
tOF 2.0 to 0.8 V, CL=15 pF
1
Output Duty Cycle (% high
time)
tOD
Measured at VDD/2,
CL=15 pF
45
50
Power Down Time, PDTS low to
clocks tri-stated
Power Up Time, PDTS high to
clocks stable
Absolute Clock Period Jitter
One sigma Clock Period Jitter
Input to output skew
tja Deviation from mean
tjs
tIO
PECLIN to CLK1,
Note 1
± 90
40
-250
Device to device skew
tpi
Common PECLIN,
measured at FBIN
0
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2.
Max.
200
160
140
55
50
10
250
500
Units
MHz
MHz
MHz
ns
ns
%
ns
ms
ps
ps
ps
ps
MDS 527-02 F
7
Revision 022806
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com