ICS341 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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ICS341 Datasheet PDF : 7 Pages
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ICS341
Field Programmable SS VersaClock Synthesizer
Parameter
Symbol
Conditions
Input Low Voltage
Output High Voltage
(CMOS High)
VIL ICLK
VOH IOH = -4 mA
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
VOH
VOL
IOS
ZO
IOH = -12 mA
IOL = 12 mA
Internal pull-up resistor
Internal pull-up resistor
Internal pull-down resistor
Input Capacitance
RPUP
RPUP
RPD
CIN
S1:S0
PDTS
CLK output
inputs
Min.
VDD-0.4
Typ.
Max.
VDD/2-1
Units
V
V
2.4
V
0.4
V
±70
mA
20
Ω
250
kΩ
250
kΩ
525
kΩ
4
pF
Note 1: Example with 25 MHz crystal input with output of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min.
Input Frequency
FIN Fundamental Crystal
5
Input Clock
2
Output Frequency
0.25
Output Rise Time
Output Fall Time
Duty Cycle
tOR 20% to 80%, Note 1
tOF 80% to 20%, Note 1
Note 2
40
Power-up time
PLL lock time from
power-up
PDTS goes high until
stable CLK output,
Spread Spectrum Off
PDTS goes high until
stable CLK output,
Spread Spectrum On
One Sigma Clock Period Jitter
Configuration Dependent
Maximum Absolute Jitter
tja
Deviation from Mean.
Configuration Dependent
Typ. Max. Units
27 MHz
50 MHz
200 MHz
1
ns
1
ns
49-51 60
%
4
10 ms
.2
2
ms
4
7
ms
50
ps
+200
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK for each PLL powered up. PDTS
transition high on select address change.
MDS 341 E
5
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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