ICS2509 Ver la hoja de datos (PDF) - Integrated Circuit Systems

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Fabricante

ICS2509

3.3V Phase-Lock Loop Clock Driver

Integrated Circuit Systems 

ICS2509C

General Layout Precautions:

An ICS2509C is used as an example. It is similar to the

ICS2510C. The same rules and methods apply.

1) Use copper flooded ground on the top signal layer

under the clock buffer The area under U1 in figure 1

on the right is an example.

2) Use power vias for power and ground. Vias 20 mil or

larger in diameter have lower high frequency

impedance. Vias for signals may be minimum drill

size.

3) Make all power and ground traces are as wide as the

via pad for lower inductance.

4) VAA for pin 23 has a low pass RC filter to decouple

the digital and analog supplies. C9-11 may be replaced

with a single low ESR (0.8 ohm or less) device with

the same total capacitance.

5) Notice that ground vias are never shared.

6) All VCC pins have a decoupling capacitor. Power is

always routed from the plane connection via to the

capacitor pad to the VCC pin on the clock buffer.

7) Component R1 is located at the clock source.

Figure 1.

Component Values:

C1= As necessary for delay adjust

C[7:2]=.01uF

C8,C13=0.1uF

C[11:9]=4.7Uf

R1=10 ohm. Locate at driver

R2=10 ohm.

6

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