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ICS1893BF Datasheet PDF : 133 Pages
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ICS1893BF Data Sheet - Release
Table of Contents
Table of Contents
Section
Chapter 7
7.1
7.1.1
7.1.2
7.1.3
7.1.4
Title
Page
Management Register Set ............................................................................................... 49
Introduction to Management Register Set ............................................................. 50
Management Register Set Outline ......................................................................... 50
Management Register Bit Access .......................................................................... 51
Management Register Bit Default Values .............................................................. 51
Management Register Bit Special Functions ......................................................... 52
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
Register 0: Control Register ................................................................................... 53
Reset (bit 0.15) ...................................................................................................... 53
Loopback Enable (bit 0.14) .................................................................................... 54
Data Rate Select (bit 0.13) ..................................................................................... 54
Auto-Negotiation Enable (bit 0.12) ......................................................................... 54
Low Power Mode (bit 0.11) .................................................................................... 55
Isolate (bit 0.10) ..................................................................................................... 55
Restart Auto-Negotiation (bit 0.9) .......................................................................... 55
Duplex Mode (bit 0.8) ............................................................................................. 56
Collision Test (bit 0.7) ............................................................................................ 56
IEEE Reserved Bits (bits 0.6:0) ............................................................................. 56
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
Register 1: Status Register .................................................................................... 57
100Base-T4 (bit 1.15) ............................................................................................ 57
100Base-TX Full Duplex (bit 1.14) ......................................................................... 58
100Base-TX Half Duplex (bit 1.13) ........................................................................ 58
10Base-T Full Duplex (bit 1.12) ............................................................................. 58
10Base-T Half Duplex (bit 1.11) ............................................................................ 58
IEEE Reserved Bits (bits 1.10:7) ........................................................................... 59
MF Preamble Suppression (bit 1.6) ....................................................................... 59
Auto-Negotiation Complete (bit 1.5) ....................................................................... 59
Remote Fault (bit 1.4) ............................................................................................ 60
Auto-Negotiation Ability (bit 1.3) ............................................................................ 60
Link Status (bit 1.2) ................................................................................................ 60
Jabber Detect (bit 1.1) ........................................................................................... 61
Extended Capability (bit 1.0) .................................................................................. 61
7.4
Register 2: PHY Identifier Register ........................................................................ 62
ICS1893BF, Rev. C, 9/29/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
4
September, 2005
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