ICL7121 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

ICL7121

16-Bit Multiplying Microprocessor-Compatible D/A Converter

Intersil 

Timing Diagram

ICL7121

FIGURE 3.

Definition of Terms

Integral Linerarity Error - Error contributed by deviation of

the DAC transfer function from a “best staight line” through

the actual plot of transfer function. Normally expressed as a

percentage of full scale range or in (sub)multiples of 1 LSB.

Differential Linearity Error - The difference between ideal

and actual value of the analog output “step size” for any two

adjacent digital input code. The ideal “step size” is equal to

2-n of full scale for an n-bit DAC or 1 LSB. It is expressed in

(sub)multiples of 1 LSB.

Resolution - It is addressing the smallest distinct analog

output change that a D/A converter can produce. It is

commonly expressed as the number of converter bits. A

converter with resolution of n bits can resolve output

changes of 2-n of the full-scale range, e.g. 2-n VREF for a

unipolar conversion. Resolution by no means implies

linearity.

Settling Time - Time required for the output of a DAC to

settle to within a specified error band around its final value

(e.g. 1/2 LSB) for a given digital input change, i.e., all digital

inputs LOW to HIGH and HIGH to LOW.

Gain Error - The difference between actual and ideal analog

output values at full-scale range, ie.e. all digital inputs at

HIGH state. It is expressed as a percentage of full-scale

range or in (sub)multiples of 1 LBB.

Output Capacitance - Capcitance from IOUT terminal to

ground.

Detailed Description

The ICL7121 consists of a 16-bit primary DAC, PROM con-

trolled correction DACs, input buffer registers, and micropro-

cessor interface logic. The 16-bit primary DAC is an R-2R

thin film resistor ladder with N-channel MOS SPDT current

steering switches. Precise balancing of the switch resis-

tances and all other resistors in the ladder results in excel-

lent temperature stability.

The low linearity error is achieved by programming a floating

polysilicon gate PROM array which controls a 12-bit correc-

tion DAC (C-DAC). The most significant bits of the primary

DAC register address this PROM array. Thus for every com-

bination of the primary DAC’s most significant bits a different

C-DAC code is selected, allowing correctino of superposition

erros. These errors are cuased by bit interaction on the pri-

mary ladder’s current bus and by voltage non-linearity in the

feedback resistor. Superposition errors cannot be corrected

by any method that corrects individual bits only, such as

laser trimming.

The onboard PROM also controls the 6-bit gain DAC. The G-

DAC reduces gain error to less than 0.006% FSR by divert-

ing to analog ground up to 2% of the current flowing in RFB.

Since the PROM programming occurs in packaged form, it

corrects for resistor shifts caused by the thermal stresses of

packaging, unlike wafer-level trimming methods. Also, since

the thin film resistors do not suffer laser trimming stresses,

no degradation of time-stability results.

Applications

Bipolar Operation

The circuit diagram for the normal configuration of the

ICL7121 is shown in Figure 1. The positive and negative

reference voltages allow full four-qudrant multiplication.

Amplifier A3, together with the internal resistors RINV1 and

RINV2, forms a simple voltage inverter circuit to generate -

VREF for the ROFS offset input pin. This will give the nominal

“digital input code/analog otuput value” relationship of Table

1. Note that the value of RFB is equal to 2R so full scale

range is 2VREF .

The offset binary transfer function can be achieved simply by

inverting the MSB. Inversion of the MSB can be done by an

inverter or may be done in software.

TABLE 1. 2’S COMPLEMENT BIPOLAR OPERATION

MSB

0111

0111

0000

DIGITAL INPUT

1111

1111

0000

1111

1111

0000

LSB

1111

1110

0001

ANALOG OUTPUT

-VREF (1 - 1/215)

-VREF (1 - 1/214)

-VREF (1/215)

7

Share Link: