ICL7112 Ver la hoja de datos (PDF) - Intersil

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ICL7112

12-Bit, High-Speed, CMOS µP-Compatible A/D Converter

Intersil 

ICL7112

Memory Access (DMA) controller as shown in Figure 8.

Applications

Figure 9 shows a typical application of the ICL7112 12- bit

A/D converter. A bipolar input voltage range of +10V to -10V

is the result of using the current through R2 to force a 1/2

scale offset on the input amplifier (A1). The output of A1

swings from 0V to -1 0V. The overall gain of the A/D is varied

by adjusting the 100Ω trim resistor, R5. Since the ICL7112 is

automatically zeroed every conversion, the system gain and

offset stability will be superb as long as a reference with a

tempco of 1ppm/oC and stable external resistors are used.

If is important to note that since the 7112’s DAC current

flows in A1, the amplifier should be a wideband (GBW >

20MHz) type to minimize errors.

The clock for the ICL7112 is taken from whatever system

clock is available and divided down to the level for a conver-

sion time of 40µs. Output data is controlled by the BUS and

A0 inputs. Here they are set for 8-bit bus operation with BUS

grounded and A0 under the control of the address decode

section of the external system.

Because the ICL7112’s internal accumulator generates

accurate output data for input signals as much as 3% greater

than full-scale, and because the converter’s OVR output

flags overrange inputs, a simple microprocessor routine can

be employed to precisely measure and correct for system

gain and offset errors. Figure 10 shows a typical data acqui-

sition system that uses a 10V reference, input signal multi-

plexer, and input signal Track/Hold amplifier. Two of the

multiplexer’s input channels are dedicated to sampling the

system analog ground and reference voltage. Here, as in

Figure 9, bipolar operation is accommodated by an offset

resistor between the reference voltage and the summing

junction of A1. A flip-flop in IC3 sets 1C2’s Track/Hold input

after the microprocessor has initiated a WR command, and

resets when EOC goes high at the end of the conversion.

The first step in the system calibration routine is to select the

multiplexer channel that is connected to system analog

ground and initiate a conversion cycle for the ICL7112. The

results represent the system offset error which comes from

the sum of the offsets from IC1, IC2, and A1. Next the chan-

nel connected to the reference voltage is selected and mea-

sured. These results, minus the system offset error,

represent the system full-scale range. A gain error correction

factor can be derived from this data. Since the lCL7112 pro-

vides valid data for inputs that exceed full-scale by as much

as 3%, the OVR output can be thought of as a valid 13th

data bit. Whenever the OVR bit is high, however, the total

12-bit result should be checked to ensure that it falls within

100% and 103% of full-scale. Data beyond 103% of full-

scale should be discarded.

Clock Considerations

The ICL7112 provides an internal inverter which is brought

out to pins OSC1 and OSC2, for crystal or ceramic resonator

oscillator operation. The clock frequency is calculated from:

fCLK = t---C---2-O---0-N-----V-

6-9

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