HV9608TS Ver la hoja de datos (PDF) - Supertex Inc
Número de pieza
componentes Descripción
Fabricante
HV9608TS Datasheet PDF : 6 Pages
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Ordering Information
DEVICE
Package Options
16-Pin TSSOP
HV9608
HV9608TS
HV9608
Absolute Maximum Ratings*
Input Voltage, VIN
-0.3V to +250V
Supply Voltage, VDD
+13.5V max
Operating Ambient Temperature Range
-40°C to +85°C
Operating Junction Temperature Range
-40°C to +125°C
Storage Temperature Range
-65° to +150°C
Power Dissipation @ 25°C, TSSOP
1000mW
*All voltages referenced to GND pin.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Electrical Characteristics (The * denotes the specifications which apply over the full operating temperature
range of -40°C < TA < +85°C, otherwise the specifications are at TA = 25°C, VD D = 10V, unless otherwise noted)
VIN_Pre-Regulator/Start-up/ VDD_Supply
Symbol
Parameter
VIN
Regulator input voltage
IIN,MAX
Maximum regulator current
VDD,REG
VDD, MAX
VDD,STOP
VDD,START
Regulator output voltage
Supply voltage range
VDD under voltage threshold
VDD startup voltage
IDD,OFF
Supply standby quiescent current
Min
12
20
9.27
7.58
8.33
Typ.
9.46
7.74
8.5
1.25
Max Units
250 V
mA
9.65 V
12
V
7.90 V
8.67 V
1.8 mA
Conditions
VIN = 24V, VDD = 9.2V
VIN [12V – 250V]
To guarantee table parameters
VDD falling
VDD rising
RT = 110 KΩ; RDT1= 80KΩ;
RDT1= 80KΩ; UVLO tied to
ground;
Under Voltage Lockout (UVLO)
Symbol
Parameter
Vth,UVLO UVLO threshold voltage
IHYS,UVLO UVLO hysteresis current
Min Typ. Max Units Conditions
1.112 1.135 1.158 V *
14
µA Guaranteed by design
GATE/AGATE_MOSFET Driver Output
Symbol
Parameter
Min Typ Max Units Conditions
tR1
Main gate rise time
tF1
Main gate fall time
40
60 nSec CLOAD = 1nF
20
30 nSec CLOAD = 1nF
tR2
Auxiliary gate rise time
40
60 nSec CLOAD = 0.5nF
tF2
Auxiliary gate fall time
20
30 nSec CLOAD = 0.5nF
RDT1, RDT2 Dead time control resistor range
40
d1
Rising edge delay from AGATE to
GATE
80
400 KΩ
105 130 nSec RDT1 = 80K
d2
Falling edge delay from GATE to
AGATE
100
400 nSec RDT2 = 80K
2
A122104
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