HV9110NG-G Ver la hoja de datos (PDF) - Supertex Inc

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Fabricante

HV9110NG-G

High-Voltage Current-Mode PWM Controller

Supertex Inc 

Test Circuits

+10V

(VDD)

(FB)

GND

(–VIN)

Error Amp ZOUT

1.0V swept 100Hz – 2.2MHz

–

+

Reference

0.1µF

60.4K

Tektronix

P6021

V1

(1 turn

secondary)

V2

40.2K

NOTE: Set Feedback Voltage so that

VCOMP = VDIVIDE ± 1mV before connecting transformer

HV9110

0.1V swept 10Hz – 1MHz

PSRR

100K1%

10.0V

100K1%

–

V1

4.00V

+

Reference

V2

0.1µF

Detailed Description

Preregulator

The preregulator/startup circuit for the HV9110 consists of

a high-voltage n-channel depletion-mode DMOS transis-

tor driven by an error amplifier to form a variable current

path between the VIN terminal and the VDD terminal. The

maximum current (about 20 mA) occurs when VDD = 0, with

current reducing as VDD rises. This path shuts off altogether

when VDD rises to somewhere between 7.8 and 9.4V, so that

if VDD is held at 10 or 12V by an external source(generally the

supply the chip is controlling). No current other than leakage

is drawn through the high voltage transistor. This minimizes

dissipation.

An external capacitor between VDD and VSS is generally

required to store energy used by the chip in the time be-

tween shutoff of the high voltage path and the VDD supply’s

output rising enough to take over powering the chip. This

capacitor should have a value of 100X or more the effective

gate capacitance of the MOSFET being driven, i.e.,

CSTORAGE ≥ 100 x (gate charge of FET at 10V ÷ 10V)

as well as very good high frequency characteristics. Stacked

polyester or ceramic caps work well. Electrolytic capacitors

are generally not suitable.

A common resistor divider string is used to monitor VDD for

both the under voltage lockout circuit and the shutoff circuit

of the high voltage FET. Setting the under voltage sense

point about 0.6V lower on the string than the FET shutoff

point guarantees that the under voltage lockout always re-

leases before the FET shuts off.

Bias Circuit

An external bias resistor, connected between the BIAS pin

and VSS is required by the HV9110 to set currents in a se-

ries of current mirrors used by the analog sections of the

chip. The nominal external bias current requirement is 15 to

20µA, which can be set by a 390KΩ to 510KΩ resistor if a

10V VDD is used, or a 510kΩ to 680KΩ resistor if VDD will be

12V. A precision resistor is not required; ± 5% is fine.

Clock Oscillator

The clock oscillator of the HV9110 consists of a ring of CMOS

inverters, timing capacitors, a capacitor discharge FET, and,

in the 50% maximum duty cycle versions, a frequency divid-

ing flip-flop. A single external resistor between the OSC IN

and OSC OUT is required to set the oscillator frequency (see

graph). For the 50% maximum duty cycle versions the Dis-

charge pin is internally connected to GND. For the 99% duty

cycle version, the Discharge pin can either be connected to

VSS directly or connected to VSS through a resistor used

to set a deadtime. One major difference exists between the

Supertex HV9110 and competitive 9110’s. On the Supertex

part, the oscillator is shut off when a shutoff command is re-

ceived. This saves about 150µA of quiescent current, which

aids in the construction of power supplies that meet CCITT

specification I-430, and in other situations where an abso-

lute minimum of quiescent power dissipation is required.

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