ICS85357AG01 Ver la hoja de datos (PDF) - Integrated Circuit Systems

Número de pieza

componentes Descripción

Fabricante

ICS85357AG01

4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS85357-01

4:1 OR 2:1

DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V /2 is

CC

generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock

swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.

VCC

CLK_IN

C1

0.1uF

R1

1K

+

V_REF -

R2

1K

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

TERMINATION FOR LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs.Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

50Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion. Figures 2A and 2B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

Zo = 50Ω

FOUT

FIN

Zo = 50Ω

50Ω

RTT =

1

((VOH + VOL) / (VCC – 2)) – 2

Zo

50Ω

VCC - 2V

RTT

FOUT

3.3V

125Ω

125Ω

Zo = 50Ω

FIN

Zo = 50Ω

84Ω

84Ω

FIGURE 2A. LVPECL OUTPUT TERMINATION

FIGURE 2B. LVPECL OUTPUT TERMINATION

85357AG-01

www.icst.com/products/hiperclocks.html

REV. A MARCH 21, 2005

6

Share Link: