ICS85357AG-01T(2001) Ver la hoja de datos (PDF) - Integrated Circuit Systems

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ICS85357AG-01T
(Rev.:2001)

4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS85357-01

4:1 OR 2:1

DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 7 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V /2 is

CC

generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.

CC

CLK_IN

C1

0.1uF

V

CC

R1

1K

+

V_REF

-

R2

1K

FIGURE 7 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

85357AG-01

www.icst.com/products/hiperclocks.html

7

REV. A JULY 16, 2001

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