ICS85357-01(2001) Ver la hoja de datos (PDF) - Integrated Circuit Systems

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ICS85357-01
(Rev.:2001)

4:1 OR 2:1 DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS85357-01

4:1 OR 2:1

DIFFERENTIAL-TO-3.3V LVPECL / ECL CLOCK MULTIPLEXER

GENERAL DESCRIPTION

The ICS85357-01 is a 4:1 or 2:1 Differential-to-

,&6

3.3V LVPECL / ECL clock multiplexer which can

HiPerClockS™ operate up to 750MHz and is a member of the

HiPerClockS™ family of High Performance Clock

Solutions from ICS. The ICS85357-01 has 4

selectable clock inputs. The CLK, nCLK pair can accept most

standard differential input levels. The device can operate

using a 3.3V LVPECL (VEE = 0V, VCC = 3.135V to 3.465V) or

3.3V ECL (V = 0V, V = -3.135V to -3.465V). The fully dif-

CC

EE

ferential architecture and low propagation delay make it

ideal for use in clock distribution circuits. The select pins have

internal pulldown resistors. Leaving one input unconnected

(pulled to logic low by the internal resistor) will transform

the device into a 2:1 multiplexer. The SEL1 pin is the most

significant bit and the binary number applied to the select pins

will select the same numbered data input (i.e., 00

selects CLK0, nCLK0).

FEATURES

• High speed differential multiplexer. The device can be

configured as either a 4:1 or 2:1 multiplexer

• 1 differential 3.3V LVPECL output

• 4 selectable CLK, nCLK inputs

• CLK, nCLK pair can accept the following differential input

levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

• Maximum output frequency up to 750MHz

• Translates any single ended input signal to 3.3V LVPECL

levels with resistor bias on nCLKx input

• Part-to-part skew: 150ps (maximum)

• Propagation delay: 1.5ns (maximum)

• LVPECL mode operating voltage supply range:

V = 3.135V to 3.465V, V = 0V

CC

EE

• ECL mode operating voltage supply range:

VCC = 0V, VEE = -3.135V to -3.465V

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM

PIN ASSIGNMENT

CLK0

nCLK0

CLK1

nCLK1

CLK2

nCLK2

CLK3

nCLK3

00

01

Q0

nQ0

10

11

SEL1 SEL0

VCC 1

20 VCC

CLK0 2 19 SEL1

nCLK0 3 18 SEL0

CLK1 4 17 VCC

nCLK1 5 16 Q0

CLK2 6 15 nQ0

nCLK2 7 14 VCC

CLK3 8 13 nc

nCLK3 9 12 nc

VEE 10 11 VEE

ICS85357-01

20-Lead TSSOP

4.40mm x 6.50mm x 0.90mm body package

G Package

Top View

85357AG-01

www.icst.com/products/hiperclocks.html

1

REV. A JULY 16, 2001

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