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HV507 Ver la hoja de datos (PDF) - Supertex Inc

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HV507 Datasheet PDF : 6 Pages
1 2 3 4 5 6
Supertex inc.
HV507
64-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
Features
Processed with HVCMOS® technology
Operating output voltages to 300V
Low power level shifting from 5.0 to 300V
Shift register speed: 8.0MHz @ VDD = 5.0V
64 latched data outputs
Output polarity and blanking
CMOS compatible inputs
Forward and reverse shifting options
General Description
The HV507 is a low voltage serial to high voltage parallel
converter with 64 push-pull outputs. This device has been
designed for use as a printer driver for electrostatic applications.
It can also be used in any application requiring multiple output,
high voltage, low current sourcing and sinking capabilities.
The device consists of a 64-bit shift register, 64 latches, and
control logic to perform the polarity select and blanking of the
outputs. A DIR pin controls the direction of data shift through
the device. With DIR grounded, DIOA is Data-In and DIOB is
Data-Out; data is shifted from HVOUT64 to HVOUT1. When DIR
is at logic high, DIOB is Data-In and DIOA is Data-Out: data is
then shifted from HVOUT1 to HVOUT64. Data is shifted through
the shift register on the low to high transition of the clock. Data
output buffers are provided for cascading devices. Operation
of the shift register is not affected by the LE (latch enable), BL
(blanking), or the POL(polarity) inputs. Transfer of data from the
shift register to the latch occurs when the LE is high. The data in
the latch is stored during LE transition from high to low.
Functional Block Diagram
POL
BL
Latch Enable
DIOA
CLOCK
64 bit
Static Shift
DIR
Register
64
Latches
DIOB
VPP
L/T
L/T
L/T
L/T
L/T = Level Translator
HVOUT1
HVOUT2
60 Additional
Outputs
HVOUT63
HVOUT64
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com

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