HT82V46 Ver la hoja de datos (PDF) - Holtek Semiconductor

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HT82V46

16-Bit, 45MSPS, 3-Channel CCD/CIS Analog Signal Processor

Holtek Semiconductor 

HT82V46

Symbol

Parameter

Test Conditions

Serial Control Interface

tSCK

SCK Period

―

tSCKH

SCK High

―

tSCKL

SCK Low

―

tSDIS

SDI Set-up Time

―

tSDIH

SDI Hold Time

―

tCKFENR

SCK Falling to SEN Rising

―

tENFCKR

SEN Falling to SCK Rising

―

tSEN

SEN Pulse Width

―

tENFSD7

SEN Falling to OD7/SDO Output the

D7 of Register Data

―

tCKFSD6

SCK Falling to OD7/SDO Output the

D6 of Register Data

―

tCKFOD7

SCK Falling to OD7/SDO Output OD7

―

Min.

83.3

37.5

37.5

6

6

12

12

60

―

―

―

Typ.

―

―

―

―

―

―

―

―

―

―

―

Max.

―

―

―

―

―

―

―

―

30

30

30

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Note: 1. Parameters are measured at 50% of the rising/falling edge.

2. In 1-channel mode, if the CDS2 falling edge is placed more than 3ns before the rising edge of ADCK, the

output amplitude of the HT82V46 will decrease.

Function Description

Introduction

The HT82V46 can sample up to three inputs, namely

VINR, VING and VINB, simultaneously. The device

then processes the sampled video signal with respect

to the video reset level or an internally/externally

generated reference level for signal processing. Each

processing channel consists of an Input Sampling

block with optional Reset Level Clamping (RLC)

and Correlated Double Sampling (CDS), an 8-bit

programmable offset DAC and a 9-bit Programmable

Gain Amplifier (PGA). The ADC then converts each

resulting analogue signal to a 16-bit digital word.

The digital output from the ADC is presented on an

8-bit wide bus. On-chip control registers determine

the configuration of the device, including the offsets

and gains applied on each channel. These registers are

programmable via a serial interface.

Internal Power-On-Reset (POR) Circuit

Internal POR Circuit is powered by AVDD and used

reset digital logic into a default state after power-

up. POR active from 0.6VTyp. of AVDD and release

at 1.2VTyp. of AVDD (or 0.7VTyp. of DVDD if AVDD

powered before DVDD). And when AVDD or DVDD

back to 0.6VTyp. then POR will active again. To ensure

the contents of the control registers are at their default

values before carrying out any other register writes it

is recommended software reset for every time power

is cycled.

Power Management

The device default is fully enabled. The Register Bit

EN allows the device to be fully powered down when

set low. Individual blocks can be powered down using

the bits in Setup Register 5. When in 1CH or 2CH

mode the unused input channels are automatically

disabled to reduce power consumption.

References

The ADC reference voltages are derived from an

internal bandgap reference, and buffered to pins

REFT and REFB, where they must be decoupled to

ground. Pin CML is driven by a similar buffer, and

also requires decoupling. The output buffer from the

RLCDAC also requires decoupling at pin VRLC/

VBIAS.

CDS/Non-CDS Processing

For CCD type input signals, containing a fixed

reference level, the signal may be processed using

Correlated Double Sampling (CDS), which will

remove pixel-by-pixel common mode noise. With

CDS processing the input waveform is sampled at

two different points in time for each pixel, once

during the reference level and once during the video

level. To sample using CDS, register bit CDS must

be set to 1 (default). This causes the signal reference

to come from the video reference level as shown in

Figure 1. The video sample is always taken on the

falling edge of the input CDS2 signal (C2S). In CDS-

mode the reference level is sampled on the falling

Rev. 1.10

6

November 24, 2011

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