HT82V46 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT82V46 Datasheet PDF : 27 Pages
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HT82V46
Symbol
Parameter
Programmable Gain Amplifier
Resolution
Gain Equation
GMAX
GMIN
Max Gain, Each Channel
Min Gain, Each Channel
Channel Matching
A/D Converter
Resolution
Speed
Full-scale Input Range
2*(VRT - VRB)
Supply Currents
Total Supply Current
Analogue Supply Current
Digital Supply Current
Power Down Mode
Test Conditions Min.
Typ.
Max.
Unit
―
―
9
―
bits
―
0.66 + PGA[8:0] * 7.34 / 511
V/V
―
―
7.5
―
V/V
―
―
0.65
―
V/V
―
―
1
5
%
―
―
LOWREF=0
LOWREF=1
―
16
―
bits
―
45
―
MSPS
2.0
V
―
―
1.2
V
―
―
160
―
mA
―
―
130
―
mA
―
―
30
―
mA
―
―
130
―
μA
Note: 1. Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-
scale input range.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
Timing Specification
AVDD=DVDD=3.3V, AVSS=DVSS=0V, TA=25°C, ADCK=45MHz unless otherwise stated.
Symbol
Parameter
Test Conditions Min.
Typ.
Max.
Unit
Clock Parameter
tADC
ADCK Period
―
22
―
―
ns
tADH
ADCK High Period
―
10
11
―
ns
tADL
ADCK Low Period
―
10
11
―
ns
tC1
CDS1 Pulse High
―
5
―
―
ns
tC2
CDS2 Pulse High
―
5
―
―
ns
tC1FC2R
CDS1 Falling to CDS2 Rising
―
0
―
―
ns
tADFC2R
ADCK Falling to CDS2 Rising
―
4
―
―
ns
tADRC2R
ADCK Rising to CDS2 Rising
―
2.5
―
―
ns
tADFC2F
tC2FADR
tADFC1R
ADCK Falling to CDS2 Falling
CDS2 Falling to ADCK Rising 2
1st ADCK Falling after CDS2
Falling to CDS1 Rising
―
4
―
―
ns
―
1
―
―
ns
―
1
―
―
ns
tPR3
3-channel Mode Pixel Rate
―
66
―
―
ns
tPR2
2-channel Mode Pixel Rate
―
44
―
―
ns
tPR1
1-channel Mode Pixel Rate
―
22
―
―
ns
tOD
Output Propagation Delay
―
LAT
Output Latency. From 1st ADCK Rising
Edge after CDS2 Falling to Data Output
―
―
8
12
ns
―
7
―
ADCK
periods
Rev. 1.10
5
November 24, 2011
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