HT46R652-100 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT46R652-100 Datasheet PDF : 47 Pages
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Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 16 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer, SP, which is neither readable nor writeable. At
the start of a subroutine call or an interrupt acknowledg-
ment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction, RET or RETI,
the contents of the program counter is restored to its
previous value from the stack. After a device reset, the
SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented, by RET or RETI, the interrupt will be serviced.
This feature prevents a stack overflow, allowing the pro-
grammer to use the structure easily. Likewise, if the
stack is full, and a ²CALL² is subsequently executed, a
stack overflow occurs and the first entry is lost as only
the most recent sixteen return addresses are stored.
Data Memory - RAM
The data memory has a structure of 431´8 bits, and is
divided into two functional groups, namely the special
function registers, 47´8 bits, and the general purpose
data memory, Bank0: 192´8 bits and Bank2: 192´8 bits
most of which are readable/writeable, although some
are read only. The special function registers are over-
lapped in every bank.
Any unused remaining space before 40H is reserved for
future expanded usage and if read will return a ²00H²
value. The Data Memory space before 40H will overlap
in each bank.
The general purpose data memory, addressed from 40H
to FFH (Bank0; BP=0 or Bank2; BP=2), is used for data
and control information under instruction commands. All
of the data memory areas can handle arithmetic, logic,
increment, decrement and rotate operations directly.
Except for some dedicated bits, each bit in the data
memory can be set and reset by ²SET [m].i² and ²CLR
[m].i². They are also indirectly accessible through mem-
ory pointer registers, MP0 and MP1.
After first setting up BP to the value of ²01H² or ²02H² to
access either bank 1 or bank 2 respectively, these banks
must then be accessed indirectly using the Memory
Pointer MP1. With BP set to a value of either ²01H² or
²02H², using MP1 to indirectly read or write to the data
memory areas with addresses from 40H~FFH, will re-
sult in operations to either bank 1 or bank 2. Directly ad-
dressing the Data Memory will always result in Bank 0
being accessed irrespective of the value of BP.
HT46R652
0 0 H In d ir e c t A d d r e s s in g R e g is te r 0
01H
M P0
0 2 H In d ir e c t A d d r e s s in g R e g is te r 1
03H
M P1
04H
BP
05H
ACC
06H
PCL
07H
TB LP
08H
TB LH
09H
R TC C
0A H
STATU S
0B H
IN T C 0
0C H
TM R 0H
0D H
TM R 0L
0E H
TM R 0C
0FH
TM R 1H
10H
TM R 1L
11H
TM R 1C
12H
PA
13H
PAC
14H
PB
15H
PBC
16H
PC
17H
PCC
18H
PD
19H
PDC
1A H
PW M 0
1B H
PW M 1
1C H
PW M 2
1D H
PW M 3
1E H
IN T C 1
1FH
20H
PW M 4
21H
PW M 5
22H
PW M 6
23H
PW M 7
24H
ADRL
25H
ADRH
26H
ADCR
27H
ACSR
28H
PW M 8
29H
PW M 9
2A H
P W M 10
2B H
P W M 11
2C H
P W M 12
2D H
P W M 13
2E H
P W M 14
2FH
P W M 15
S p e c ia l P u r p o s e
D a ta M e m o ry
3FH
40H
G e n e ra l P u rp o s e
D a ta M e m o ry
(3 8 4 B y te s )
FFH
:U nused
R e a d a s "0 0 "
RAM Mapping
Rev. 1.00
10
December 19, 2006
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