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HT46R23

A/D Type 8-Bit MCU

Holtek Semiconductor 

HT46R23/HT46C23

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 8 return ad-

dresses are stored).

Data Memory - RAM

The data memory is designed with 224´8 bits. The

data memory is divided into two functional groups: spe-

cial function registers and general purpose data mem-

ory (192´8). Most are read/write, but some are read

only.

The special function registers include the indirect ad-

dressing registers (00H;02H), timer/event counter

higher-order byte register (TMRH;0CH), timer/event

counter low-order byte register (TMRL;0DH),

timer/event counter control register (TMRC;0EH), pro-

gram counter lower-order byte register (PCL;06H),

memory pointer registers (MP0;01H, MP1;03H), accu-

mulator (ACC;05H), table pointer (TBLP;07H), table

higher-order byte register (TBLH;08H), status register

(STATUS;0AH), interrupt control register 0 (INTC0;

0BH), PWM data register (PWM0;1AH, PWM1;1BH),

the I2C Bus slave address register (HADR;20H), the I2C

Bus control register (HCR;21H), the I2C Bus status reg-

ister (HSR;22H), the I2C Bus data register (HDR;23H),

the A/D result lower-order byte register (ADRL;24H), the

A/D result higher-order byte register (ADRH;25H), the

A/D control register (ADCR;26H), the A/D clock setting

register (ACSR;27H), I/O registers (PA;12H, PB;14H,

PC;16H, PD;18H) and I/O control registers (PAC;13H,

PBC;15H, PCC;17H, PDC;19H). The remaining space

before the 40H is reserved for future expanded usage

and reading these locations will get ²00H². The general

purpose data memory, addressed from 40H to FFH, is

used for data and control information under instruction

commands.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP0;01H/MP1;03H).

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] or [02H] will access data memory

pointed to by MP0[01H] or MP1[03H] respectively.

Reading location 00H or 02H itself indirectly will return

the result 00H. Writing indirectly result in no operation.

The memory pointer registers (MP0 and MP1 are 8-bit

registers).

Accumulator

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

00H

In d ir e c t A d d r e s s in g R e g is te r 0

01H

M P0

02H

In d ir e c t A d d r e s s in g R e g is te r 1

03H

M P1

04H

05H

ACC

06H

PCL

07H

TB LP

08H

TB LH

09H

0A H

STATU S

0B H

IN T C 0

0C H

TM R H

0D H

TM R L

0E H

TM R C

0FH

10H

11H

12H

PA

13H

PAC

14H

PB

15H

PBC

16H

PC

17H

PCC

18H

PD

19H

PDC

1A H

PW M 0

1B H

PW M 1

1C H

1D H

1E H

IN T C 1

1FH

20H

HADR

21H

HCR

22H

HSR

23H

HDR

24H

ADRL

25H

ADRH

26H

ADCR

27H

ACSR

28H

S p e c ia l P u r p o s e

D ATA M EM O R Y

3FH

40H

G e n e ra l P u rp o s e

D ATA M EM O R Y

:U nused

(1 9 2 B y te s )

R e a d a s "0 0 "

FFH

RAM Mapping

Rev. 1.60

8

May 3, 2004

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