HT46R14 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT46R14 Datasheet PDF : 47 Pages
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HT46R14
The A/D converter request flag (ADF), the Timer/Event
Counter 1 interrupt request flag (T1F), the Timer/Event
Counter 0 interrupt request flag (T0F), enable A/D con-
verter interrupt bit (EADI), enable Timer/Event Counter
1 interrupt bit (ET1I), and enable Timer/Event Counter 0
interrupt bit (ET0I), constitute the Interrupt Control regis-
ter 1 (INTC1) which is located at 1EH in the RAM.
EMI, EEI0, EEI1, EC0I, ET0I, ET1I, and EADI are all
used to control the enable/disable status of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (EI0F, EI1F,
C0F, T0F, T1F, ADF) are all set, they remain in the
INTC1 or INTC0 respectively until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V DD
O SC1
O SC1
O SC2
fS Y S /4
O SC2
N M O S O p e n D r a in
C r y s ta l O s c illa to r
R C O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores an external sig-
nal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of oscil-
lation may vary with VDD, temperatures and the chip it-
self due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resona-
tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating fre-
quency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 65ms@5V. The WDT oscillator
can be disabled by options to conserve power.
Watchdog Timer - WDT
The clock source of the WDT is implemented by a dedi-
cated RC oscillator (WDT oscillator) or instruction clock
(system clock divided by 4) determined by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The watchdog timer can be disabled by
option. If the watchdog timer is disabled, all the execu-
tions related to the WDT result in no operation.
Once an internal WDT oscillator (RC oscillator with a pe-
riod of 65ms/@5V normally) is selected, it is divided by
213, 214 , 215 or 216 (by options) to get the WDT time-out
period. The minimum WDT time-out period is about
600ms. This time-out period may vary with temperature,
VDD and process variations. By selection the WDT op-
tions, longer time-out periods can be realized. If the
WDT time-out is selected to fS/216, the maximum
time-out period is about 4.7s.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the Halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
S y s te m C lo c k /4
W DT
O SC
M a s k fs
o p tio n
s e le c t
W D T C le a r
D iv id e r
fs/2 8
W D T P r e s c a le r
M a s k O p tio n
Watchdog Timer
T im e - o u t R e s e t
fs/2 1 6
fs/2 1 5
fs/2 1 4
fs/2 1 3
Rev. 1.00
11
November 1, 2005
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