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HT46R12A

A/D Type 8-Bit OTP MCU

Holtek Semiconductor 

HT46R12A

interrupt nesting. Other interrupt requests may happen

during this interval but only the interrupt request flag is

recorded. If a certain interrupt requires servicing within

the service routine, the EMI bit and the corresponding bit

of INTC0 and INTC1 may be set to allow interrupt nest-

ing. If the stack is full, the interrupt request will not be ac-

knowledged, even if the related interrupt is enabled, until

the stack pointer is decremented. If immediate service is

desired, the stack must be prevented from becoming full.

All these kind of interrupts have a wake-up capability. As

an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

are altered by the interrupt service program which cor-

rupts the desired control sequence, the contents should

be saved in advance.

The Comparator 0 output interrupt is initialised by set-

ting the Comparator 0 output interrupt request flag (C0F;

bit 4 of INTC0), which is caused by a falling edge transi-

tion from the Comparator 0 output. After the interrupt is

enabled, and the stack is not full, and the C0F bit is set,

a subroutine call to location 04H occurs. The related in-

terrupt request flag, C0F, is reset, and the EMI bit is

cleared to disable further maskable interrupts.

The Comparator 1 output interrupt is initialised by set-

ting the Comparator 1 output Interrupt request flag

(C1F; bit 5 of the INTC0), which is caused by a falling

edge transition from the Comparator 1 output. After the

interrupt is enabled, and the stack is not full, and the

C1F bit is set, a subroutine call to location 08H occurs.

The related interrupt request flag, C1F, is reset, and the

EMI bit is cleared to disable further maskable interrupts.

The external interrupt is triggered by a failing edge on

PC1 and the related request flag, EIF, is also set. After

the interrupt is enabled, the stack is not full, and the ex-

ternal interrupt is active, a subroutine call occurs. The

interrupt request flag, EIF, is reset and the EMI bit is

cleared to disable further interrupts.

The internal Timer/Event Counter 0 interrupt is initialised

by setting the Timer/Event Counter 0 interrupt request

flag (T0F; bit 4 of the INTC1), caused by a timer overflow.

When the interrupt is enabled, the stack is not full and the

T0F bit is set, a subroutine call to location 010H will occur.

The related interrupt request flag, T0F, will be reset and

the EMI bit cleared to disable further interrupts.

The internal Timer/Event Counter 1 is operated in the

same manner. The Timer/Event Counter 1 related inter-

rupt request flag is T1F (bit 5 of the INTC1) and its sub-

routine call location is 014H. The related interrupt

request flag, T1F, will be reset and the EMI bit cleared to

disable further interrupts.

Bit No.

0

1

2

3

4

5

6

7

Label

EMI

EC0I

EC1I

EEI

C0F

C1F

EIF

¾

Function

Controls the master (global) interrupt (1=enable; 0=disable)

Controls the Comparator 0 interrupt (1=enable; 0=disable)

Controls the Comparator 1 interrupt (1=enable; 0=disable)

Control external interrupt (1=enabled, 0=disabled)

Comparator 0 request flag (1=active; 0=inactive)

Comparator 1 request flag (1=active; 0=inactive)

External interrupt flag (1=active, 0=inactive)

Unused bit, read as ²0²

INTC0 (0BH) Register

Bit No.

0

1

2

3

4

5

6

7

Rev. 1.00

Label

ET0I

ET1I

EADI

¾

T0F

T1F

ADF

¾

Function

Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)

Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)

Controls the A/D converter interrupt (1=enable; 0=disable)

Unused bit, read as ²0²

Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)

Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)

A/D converter request flag (1=active; 0=inactive)

Unused bit, read as ²0²

INTC1 (1EH) Register

10

August 3, 2007

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