HT48C062 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT48C062 Datasheet PDF : 31 Pages
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HT48R062/HT48C062
Functional Description
Execution Flow
The HT48R062/HT48C062 system clock can be derived
from a crystal/ceramic resonator oscillator or an RC. It is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter - PC
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 1024 ad-
dresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set or return from subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
In s tr u c tio n C y c le
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
*9
Initial Reset
0
Skip
Loading PCL
*9
Jump, Call Branch
#9
Return from Subroutine
S9
Note: *9~*0: Program counter bits
#9~#0: Instruction code bits
Program Counter
*8
*7
*6
*5
*4
*3
*2
*1
*0
0
0
0
0
0
0
0
0
0
Program Counter+2
*8 @7 @6 @5 @4 @3 @2 @1 @0
#8 #7 #6 #5 #4 #3 #2 #1 #0
S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
S9~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.21
4
December 30, 2008
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