HT48CA6 Ver la hoja de datos (PDF) - Holtek Semiconductor
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HT48CA6 Datasheet PDF : 31 Pages
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HT48CA6
The chip reset status of the registers is summarized in the following table:
Register
WDT Time-out
(Norma Operation)
RES Reset
(Normal Operation)
PC (Program Counter)
000H
000H
MP
-uuu uuuu
-uuu uuuu
ACC
uuuu uuuu
uuuu uuuu
TBLP
uuuu uuuu
uuuu uuuu
TBLH
--uu uuuu
--uu uuuu
STATUS
--1u uuuu
--uu uuuu
PA
1111 1111
1111 1111
PB
1111 1111
1111 1111
PC
---- ---1
---- ---1
Note: ²u² means ²unchanged²
²x² means ²unknown²
RES Reset
(HALT)
000H
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--01 uuuu
1111 1111
1111 1111
---- ---1
Carrier
The HT48CA6 provides a carrier output which shares
the pin with PC0. It can be selected to be a carrier output
(REM) or level output pin (PC0) by mask option. If the
carrier output option is selected, setting PC0=²0² to en-
able carrier output and setting PC0=²1² to disable it at
high level output.
The clock source of the carrier is implemented by in-
struction clock (system clock divided by 4) and pro-
cessed by a frequency divider to yield various carry
frequency.
Clock Source
Carry Frequency=
m ´ 2n
C lo c k S o u r c e
( S y s te m C lo c k /4 )
. r e q u e n c y D iv id e r
3 - b it C o u n te r
1 /2
M a s k O p tio n
1 /3
where m=2 or 3 and n=0~3, both are selected by mask
option. If m=2, the duty cycle of the carrier output is 1/2
duty. If m=3, the duty cycle (active low) of the carrier out-
put can be 1/2 duty or 1/3 duty also determined by mask
option (with the exception of n=0).
Detailed selection of the carrier duty is shown below:
m´2n
Duty Cycle (Active Low)
2, 4, 8, 16
1/2
3
1/3
6, 12, 24
1/2 or 1/3
V
DD
M
(c a
ask
r r ie r
op
or
tio n
le v e
l)
1 /2 o r 1 /3 d u ty
Level
C a r r ie r D u ty
S e le c t
C a r r ie r
R E M /P C 0
R e a d p a th fo r r e a d - m o d ify - w r ite
Carrier/Level output
P C 0 D a ta R e g is te r
R e a d D a ta
D ATA BU S
S y s te m W a k e -u p
M a s k O p tio n
PB input lines
V DD
P u ll- u p
P B 2~P B 7
Rev. 1.10
9
July 26, 2002
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