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HT48RA0-1 Datasheet PDF : 33 Pages
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HT48RA0-1/HT48CA0-1
The chip reset status of the registers is summarized in the following table:
Register
Reset
WDT Time-out
RES Reset
(Power On) (Normal Operation) (Normal Operation)
Program Counter
000H
000H
000H
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
PA
1111 1111
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
PC
---- ---1
---- ---1
---- ---1
RES Reset
(HALT)
000H
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--01 uuuu
1111 1111
1111 1111
---- ---1
WDT Time-out
(HALT)*
000H
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--11 uuuu
uuuu uuuu
uuuu uuuu
---- ---u
Note: ²u² means unchanged
²x² means unknown
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem powers up or when the system awakes from a HALT
state.
When a system power up occurs, an SST delay is added
during the reset period. But when the reset comes from
the RES pin, the SST delay is disabled. Any wake-up
from HALT will enable the SST delay.
The functional unit chip reset status is shown below.
Program Counter
WDT Prescaler
Input/Output ports
Stack Pointer
Carrier output
000H
Clear
Input mode
Points to the top of the stack
Low level
Carrier
The HT48RA0-1/HT48CA0-1 provides a carrier output
which shares the pin with PC0. It can be selected to be a
carrier output (REM) or level output pin (PC0) by code
option. If the carrier output option is selected, setting
PC0=²0² to enable carrier output and setting PC0=²1² to
disable it at low level output.
The clock source of the carrier is implemented by in-
struction clock (system clock divided by 4) and pro-
cessed by a frequency divider to yield various carry
frequency.
Clock Source
Carry Frequency=
m´ 2n
where m=2 or 3 and n=0~3, both are selected by code
option. If m=2, the duty cycle of the carrier output is 1/2
duty. If m=3, the duty cycle of the carrier output can be
1/2 duty or 1/3 duty also determined by code option (with
the exception of n=0).
Detailed selection of the carrier duty is shown below:
m´2n
Duty Cycle
2, 4, 8, 16
1/2
3
1/3
6, 12, 24
1/2 or 1/3
The following table shows examples of carrier fre-
quency selection.
fSYS
fCARRIER
Duty
m´2n
37.92kHz
1/3 only
3
455kHz
56.9kHz
1/2 only
2
C lo c k S o u r c e
( S y s te m C lo c k /4 )
F r e q u e n c y D iv id e r
3 - b it C o u n te r
C o d e O p tio n
V DD
1 /2 o r 1 /3 d u ty
Level
1 /2
C a r r ie r D u ty
S e le c t
1 /3
C a r r ie r
R e a d p a th fo r r e a d - m o d ify - w r ite
Carrier/Level Output
C o d e O p tio n
( c a r r ie r o r le v e l)
C a r r ie r
Level
P C 0 D a ta R e g is te r
R E M /P C 0
Rev. 1.40
9
December 21, 2005
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