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HT48RA0-1

Remote Type 8-Bit MCU

Holtek Semiconductor 

HT48RA0-1/HT48CA0-1

Input/Output Ports

There are an 8-bit bidirectional input/output port, a 6-bit

input with 2-bit I/O port and one-bit output port in the

HT48RA0-1/HT48CA0-1, labeled PA, PB and PC which

are mapped to [12H], [14H], [16H] of the RAM, respec-

tively. Each bit of PA can be selected as NMOS output or

Schmitt trigger with pull-high resistor by software in-

struction. PB0~PB1 have the same structure with PA,

while PB2~PB7 can only be used for input operation

(Schmitt trigger with pull-high resistors). PC is only

one-bit output port shares the pin with carrier output. If

the level option is selected, the PC is CMOS output.

Both PA and PB for the input operation, these ports are

non-latched, that is, the inputs should be ready at the T2

rising edge of the instruction ²MOV A, [m]² (m=12H or

14H). For PA, PB0~PB1 and PC output operation, all

data are latched and remain unchanged until the output

latch is rewritten.

When the PA and PB0~PB1 is used for input operation,

it should be noted that before reading data from pads, a

²1² should be written to the related bits to disable the

NMOS device. That is, the instruction ²SET [m].i² (i=0~7

for PA, i=0~1 for PB) is executed first to disable related

NMOS device, and then ²MOV A, [m]² to get stable data.

After chip reset, PA and PB remain at a high level input

line while PC remain at high level output, if the level op-

tion is selected.

Each bit of PA, PB0~PB1 and PC output latches can be

set or cleared by the ²SET [m].i² and ²CLR [m].i²

(m=12H, 14H or 16H) instructions respectively.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR [m]²,

²CPL [m]², ²CPLA [m]² read the entire port states into

the CPU, execute the defined operations (bit-operation),

and then write the results back to the latches or to the

accumulator.

Each line of PB has a wake-up capability to the device

by code option. The highest seven bits of PC are not

physically implemented, on reading them a ²0² is re-

turned and writing results in a no-operation.

D a ta b u s

D

Q

V DD

W eak

P u ll- u p

W r ite

C h ip R e s e t

CK Q

S

R e a d D a ta

S y s te m W a k e -u p

C o d e O p tio n

P B 0 ~ P B 1 o n ly

PA, PB Input/Output Lines

P A 0~P A 7

P B 0~P B 1

R e a d D a ta

D a ta b u s

S y s te m W a k e -u p

C o d e O p tio n

PB Input Lines

V DD

P u ll- u p

P B 2~P B 7

Rev. 1.40

10

December 21, 2005

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