HT1380A Ver la hoja de datos (PDF) - Holtek Semiconductor

Número de pieza

componentes Descripción

Fabricante

HT1380A

Step Counter

Holtek Semiconductor 

HT1380A/HT1381A

The following diagram shows the single and burst mode transfer:

Single Byte Transfer

S C LK

REST

I/O

0 1 2 3 4 5 6 701 2 3 4 5 67

R /W A 0 A 1 A 2 0 0 0 1

C o m m a n d B y te

D a ta I/O

Burst Mode Transfer

S C LK

REST

I/O

012345670

7

R /W 1 1 1 1 1 0 1

C o m m a n d B y te

D a ta B y te 0

0

7

D a ta B y te 7

Crystal Specifications

Symbol

Parameter

fO

ESR

CL

Nominal Frequency

Series Resistance

Load Capacitance

Min.

Typ.

Max.

Unit

—

32.768

—

kHz

—

—

50

kΩ

—

9.0

—

pF

Note: 1. It is strongly recommended to use a crystal with a load capacitance of 9.0pF. Never use a crystal with a

load capacitance of 12.5pF.

2. The oscillator selection can be optimized using a high quality resonator with a small ESR value. Refer to

the crystal manufacturer for more details: www.microcrystal.com.

Operating Flowchart

To initiate any transfer of data, REST is taken high and

an 8-bit command byte is first loaded into the control

logic to provide the register address and command

information. Following the command word, the clock/

calendar data is serially transferred to or from the

corresponding register. The REST pin must be taken

low again after the transfer operation is completed. All

data enter on the rising edge of SCLK and outputs on

the falling edge of SCLK. In total, 16 clock pulses are

needed for a single byte mode and 72 for burst mode.

Both input and output data starts with bit 0.

In using the HT1380A/HT1381A, set first the WP and

CH to 0 and wait for about 3 seconds, the oscillator

will generate the clocks for internal use. Then, choose

either single mode or burst mode to input the data.

The read or write operating flowcharts are shown on

the next page.

Rev. 1.00

7

June 15, 2012

Share Link: