HSP45240 Ver la hoja de datos (PDF) - Intersil

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HSP45240

Address Sequencer

Intersil 

HSP45240

ODx - Output Delay: Delays OUTO-1 1 from OUT12-23 by SDx - Start Delay: Delays the “START” by the decoded num-

the following number of clocks.

ber of clocks.

OD2

0

0

0

0

1

1

1

1

OD1

0

0

1

1

0

0

1

1

OD0

0

1

0

1

0

1

0

1

Output Delay of 0.

Output Delay of 1.

Output Delay of 2.

Output Delay of 3.

Output Delay of 4.

Output Delay of 5.

Output Delay of 6.

Output Delay of 7.

DS - Dual Sequencer Enable: Allows two independent 12-

bit sequences to be generated.

0

A 24-bit sequence is generated.

1

Two 12-bit sequences are generated.

Mx - Mode: Sequencer Mode.

M1

M0

0

0

One-Shot Mode without Restart.

0

1

One-Shot Mode with Restart.

1

x

Continuous Mode (x = don’t care).

During reset, this register will be reset to all zeroes. This will

configure the chip as a 24-bit sequencer with zero delays on

the outputs. The chip will also be in one-shot mode without

restart.

Start Delay Control Register

The Start Delay Control Register is used to configure the

start circuitry for delayed starts from 1 to 31 clock cycles.

Internal “START”, external “START”, and restarts will be

delayed by the programmed amount. The structure of the

Start Delay Control Register is shown in Table 3.

TABLE 3. START DELAY CONTROL REGISTER FORMAT

D5

SDE

ADDRESS LOCATION: 1x110110

D4

D3

D2

D1

D0

SD4

SD3

SD2

SD1 SD0

SD4 SD3 SD2 SD1 SD0

0

0

0

0

1 Start Delay of 1.

0

0

0

1

0 Start Delay of 2.

0

0

0

1

1 Start Delay of 3.

1

1

1

1

1 Start Delay of 31.

During reset, this register will be reset to all zeros. This will

bring the chip up in a mode with Start Delay disabled.

Test Control Register

A Test Control Register is provided to configure the

sequence generator to produce test sequences. In this

mode, the sequence generator can be configured to multi-

plex out the contents of the down counters in the sequence

generator control circuitry, Figure 2. These counters are

used to determine when a block or sequence is complete. As

shown in Figures 1 and 2, the MSW or LSW in the down

counters is multiplexed to the MSW of the address generator

output. In addition, a test mode is provided in which the

sequence generator performs a shifting operation on the

contents of the start address register. The structure of the

Test Control Register is shown in Table 4.

REGISTERED

BLOCK SIZE

DC

OO

WU

NN

T

E

R

#

1

REGISTERED

NUMBER OF

BLOCKS

DC

OO

WU

NN

T

E

R

#

2

TO ADDRESS

GENERATION SECTION

12

MUX

MUX CONTROLS/

REGISTER ENABLES

24

24

24

24

CONTROL

DONE

BLOCKDONE

DLYBLK

“START”

REGISTERED

MODE

FIGURE 2. SEQUENCE GENERATOR CONTROL

SDE - Start Delay Enable: Enables “START” to be delayed

by the programmed amount. When Start Delay is enabled, a

minimum of “1” is required for the programmed delay.

0

Start Delay is Disabled.

1

Start Delay is Enabled.

TABLE 4. TEST CONTROL REGISTER FORMAT

ADDRESS LOCATION: 1x110101

D5

D4

D3

D2

D1

D0

xx

xx

SE

COE

CS1

CS0

Bits “D5” and “D6” are currently not used.

SE - Shifter Enable: Input to crosspoint switch is generated

by shifting Start Address Register one bit per clock.

7

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