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HSP45240

Address Sequencer

Intersil 

HSP45240

CURRENT

BLOCK

START

ADDRESS

STEP SIZE

START

ADDRESS

BLOCK

STEP SIZE

BLOCK

SIZE

NUMBER

OF

BLOCKS

MODE

R

E

G

M

U

X

R

1

E

G

“0”

R

E

G

M

U

X

R

“0”

2

E

G

12 MSB

HOLDING

REGISTER

M 12

A

U

D

X

R 24

D

E

E

12 LSB

G

R

TO

CROSS-

POINT

SWITCH

12

ADDRESS

GENERATION

R

E

TEST MODE

MUX CONTROLS/

CONTROL

DATA

REGISTER ENABLES

G

DONE

R

SEQUENCE

E

GENERATOR

BLOCKDONE

G

CONTROL

DLYBLK

R

E

G

“START”

FIGURE 1. SEQUENCE GENERATOR BLOCK

Three modes of operation may be selected by loading the 6-bit

Mode Control register (see Processor Interface). The three

modes of operation are:

1. One-Shot Mode without Restart Address generation halts

after completion of the user specified address sequence.

Address generation will not resume until the internal

START signal is generated by the Start Circuitry. When the

final address in the final block of the address sequence is

generated, both DONE and BLOCKDONE are asserted

and the last address is held on OUT0-23 (See Application

Note 9205).

2. One-Shot Mode with Restart: This mode is identical to

One-Shot Mode without Restart with the exception that the

Start Circuitry automatically generates an internal START

at the end of the user specified sequence to restart ad-

dress generation. The end of the address sequence is sig-

naled by the assertion of DONE, BLOCKDONE, and

STARTOUT as shown in Application Note 9205. In this

mode, the first address of the next sequence immediately

follows the last address of the current sequence if start de-

lay is disabled.

3. Continuous Mode: Address generation never terminates.

Address generation proceeds based on the Start Address,

Address Increment, Block Size, and Block Increment Pa-

rameters. The Number of Blocks parameter is ignored,

and the DONE signal is never asserted.

The Mode Control register is also used to configure the

Sequence Generator for operation as two independent 12-bit

address sequencers. In dual sequencer mode, the adder in

the sequence generator suppresses the carry from the 12

LSBs to the 12 MSBs. With the carry suppressed, two inde-

pendent sequences may be produced. These 12-bit address

sequences may be delayed relative to each other by program-

ming the Mode Control register for a delay up to 7 clocks. This

feature is useful to compensate for pipeline delay when using

dual sequencer mode to generate read/write addressing.

The DLYBLK input can be used to halt address generation at

the end of any address block within a sequence. In addition,

DLYBLK can be used to delay an address sequence from

restarting if asserted at the end of the final address block gen-

erated under “One-Shot Mode with Restart”. See Application

Note 9205 for the timing relationship of DLYBLK to the end of

the address block required to halt address sequencing.

Crosspoint Switch

The crosspoint switch is responsible for reordering the

address bits output by the sequence generator. The switch

allows any of its 24 inputs to be independently connected to

any of its 24 outputs. The crosspoint switch outputs can be

driven by only one input, however, one input can drive any

number of switch outputs. If none of the inputs are mapped to

a particular output bit, that output will be “low”.

The input to output map is configured through the processor

interface. The I/O map is stored in a bank of 24 configuration

registers. Each register corresponds to one output bit. The

output bit is mapped to the input via a value, 0 to 23, stored in

the register. After power-up, the user has the option of config-

uring the switch in 1:1 mode by using the reset input, “RST”.

In 1:1 mode the crosspoint switch outputs are in the same

order as the input. More details on configuring the switch reg-

isters are contained in the Processor Interface text.

5

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