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Fabricante

HSP45240

Address Sequencer

Intersil 

Pin Descriptions

NAME

OEL

STARTIN

TYPE

I

I

DLYBLK

I

OUT0-23

O

BLOCK DONE

O

DONE

O

ADDVAL

O

START-OUT

O

BUSY

O

NOTE: #Denotes active low.

HSP45240

PLCC

PIN

NUMBER

DESCRIPTION

29

OUTPUT ENABLE LOW: This asynchronous input is used to enable the output buffers

for OUT0-11.

31

START-IN: This active low input initiates an addressing sequence. May be tied to

STARTOUT of another H5P45240 for multichip synchronization. STARTIN should only

be asserted for one CLK because address sequencing begins after STARTIN is deas-

serted.

30

DELAY BLOCK: This active “high” input may be used to halt address generation on ad-

dress block boundaries (see Sequence Generator text). The required timing relation-

ship of this signal to the end of an address block is shown in Application Note 9205.

39, 40, 42, 45,

47, 48, 50, 51,

53, 54, 56, 57,

59, 62-64, 66,

67, 1, 2, 4, 5,

7, 8

OUTPUT BUS: TTL compatible 24-bit Address Sequencer output.

36

BLOCK DONE: This active low output signals when the last address in an address

block is on OUT0-23.

37

DONE: This active low output signals when the last address of an address sequence is

on OUT0-23.

33

ADDRESS VALID: This active low output signals when the first address of an address

sequence is on 0UT0-23.

32

START-OUT: This active low output is generated when an address sequence is initiat-

ed by a mechanism other than STARTIN. May be tied to the STARTIN of other

H5P45240’s for multichip synchronization.

35

BUSY: This active low output is asserted one CLK after RST is deasserted and will re-

main asserted for 25 CLK’s. While BUSY is asserted, all writes to the Processor Inter-

face are disabled.

3

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