HSP45240 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

HSP45240

Address Sequencer

Intersil 

Pinouts

HSP45240

ADDRESS SEQUENCER HSP45240

68 PIN PLASTIC LEADED CHIP CARRIER (PLCC)

NC

D0

D1

D2

D3

D4

D5

D6

GND

WR

A0

CS

GND

CLK

VCC

RST

NC

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

10

60

11

59

12

58

13

57

14

56

15

55

16

54

17

53

18

52

19

51

20

50

21

49

22

48

23

47

24

46

25

45

26

44

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

NC

OUT12

GND

OUT11

OUT10

VCC

OUT9

OUT8

GND

OUT7

OUT6

VCC

OUT5

OUT4

GND

OUT3

NC

Pin Descriptions

NAME

VCC

GND

TYPE

I

I

RST

I

CLK

I

WR

I

CS

I

A0

I

D0-6

I

OEH

I

PLCC

PIN

NUMBER

DESCRIPTION

6, 24, 34, 41 +5V power supply pin.

49, 55, 68

3, 9, 18, 22,

38, 46, 52,

58, 65

GROUND.

25

RESET: This active low input causes a chip reset which lasts for 26 clocks after RST

has been deasserted. The reset initializes the Crosspoint Switch and some of the con-

figuration registers as described in the Processor Interface Section. The chip must be

clocked for reset to complete.

23

CLOCK: The “CLK” signal is a CMOS input which provides the basic timing for address

generation.

19

WRITE: The rising edge of this input latches the data/address on D0-6 to be latched into

the Processor Interface.

21

CHIP SELECT: This active “low” input enables the configuration data/address on

D0-6 to be latched into the Processor Interface.

20

ADDRESS 0: This input defines D0-6 as a configuration register address if “high”, and

configuration data if “low”, (see Processor Interface text).

11-17

DATA BUS: Data bus for Processor Interface.

28

OUTPUT ENABLE HIGH: This asynchronous input is used to enable the output buffers

for OUT 12-23.

2

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