HM-6504/883 Ver la hoja de datos (PDF) - Intersil
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HM-6504/883 Datasheet PDF : 10 Pages
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HM-6504/883
TABLE 2. HM-6504/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
Chip Enable
Access Time
(1) TELQV
Address Access
Time
(2) TAVQV
Chip Enable
Pulse Negative
Width
(5) TELEH
Chip Enable
Pulse Positive
Width
(6) TEHEL
Address Setup
Time
(7) TAVEL
Address Hold
Time
(8) TELAX
Write Enable
Pulse Width
(9) TWLWH
Write Enable
Pulse Setup
Time
(10) TWLEH
Early Write Pulse (11) TWLEL
Setup Time
Early Write Pulse (13) TELWH
Hold Time
Data Setup Time (14) TDVWL
Early Write Data
Setup Time
Data Hold Time
(15) TDVEL
(16) TWLDX
Early Write Data
Hold Time
Read or Write
Cycle Time
(17) TELDX
(18) TELEL
(NOTES 1, 2)
CONDITIONS
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V, Note 3
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
VCC = 4.5 and
5.5V
GROUP
A SUB-
GROUPS
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERA-
TURE
-≤55+o1C25≤oTCA
-55oC ≤ TA
≤ +125oC
-55oC ≤ TA
≤ +125oC
HM-6504S/883
MIN MAX
-
120
-
120
120
-
LIMITS
HM-6504B/883
MIN MAX
-
200
-
220
200
-
HM-6504/883
MIN MAX
-
300
-
320
300
-
9, 10, 11 -55oC ≤ TA 50
-
90
-
120
-
≤ +125oC
9, 10, 11 -55oC ≤ TA
0
≤ +125oC
9, 10, 11 -55oC ≤ TA 40
≤ +125oC
9, 10, 11 -≤55+o1C25≤oTCA
20
9, 10, 11 -≤55+o1C25≤oTCA
70
-
20
-
20
-
-
50
-
50
-
-
60
-
80
-
-
150
-
200
-
9, 10, 11 -55oC ≤ TA
0
-
0
-
0
-
≤ +125oC
9, 10, 11 -55oC ≤ TA 40
-
60
-
80
-
≤ +125oC
9, 10, 11 -55oC ≤ TA
0
-
0
-
0
-
≤ +125oC
9, 10, 11 -55oC ≤ TA
0
-
0
-
0
-
≤ +125oC
9, 10, 11 -55oC ≤ TA 25
-
60
-
80
-
≤ +125oC
9, 10, 11 -55oC ≤ TA 25
-
60
-
80
-
≤ +125oC
9, 10, 11 -55oC ≤ TA 170
-
290
-
420
-
≤ +125oC
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
6-137
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