BR93LC66 Ver la hoja de datos (PDF) - ROHM Semiconductor
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BR93LC66 Datasheet PDF : 12 Pages
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Memory ICs
BR93LC66 / BR93LC66F / BR93LC66RF / BR93LC66FV
CS
SK
12
4
DI
1 0 1 A7 A6
DO
High-Z
11 12
A1 A0 D15 D14
tCS
27
D1 D0
Fig.4 Write cycle timing (WRITE)
STATUS
tSV
BUSY READY
tE / W
CS
tCS
STATUS
SK
12
5
12
27
DI
1 0 00
DO
High-Z
D15 D14
D1 D0
Fig.5 Write all address cycle timing (WRAL)
tSV
BUSY READY
tE / W
(STATUS)
After time tCS following the fall of CS, after input of the
write command), if CS is set to HIGH, the write execute
= BUSY (LOW) and the command wait status READY
(HIGH) are output.
If in the command wait status (STATUS = READY), the
next command can be performed within the time tE / W.
Thus, if data is input via SK and DI with CS = HIGH in
the tE / W period, erroneous operations may be per-
formed. To avoid this, make sure that DI = LOW when
CS = HIGH. (Caution is especially important when
common input ports are used.) This applies to all of the
write commands.
CS
SK
(7) All address write (Figure 5)
With this command, the input 16-bit data is written
simultaneously to all of the addresses (128 words).
Rather than writing one word at a time, in succession,
data is written all at one time, enabling a write time of
tE / W.
(8) Write disable (Figure 6)
When the power supply is turned on, the IC enters the
write disable status. Similarly, when a write disable
command is issued, the IC enters the same status.
When in this status, all write commands are ignored,
but read commands may be executed.
In the write enable status, writing begins even if a write
command is entered accidentally. To prevent errors of
this type, we recommend executing a write disable
command after writing has been completed.
DI
1 000 0
DO
High-Z
Fig.6 Write disable cycle timing (WDS)
8
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