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5962-88690013A Datasheet PDF : 8 Pages
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HM-6642
Programming
Introduction
The HM-6642 is a 512 word by 8-bit field Programmable
Read Only Memory utilizing nicrome fusible links as pro-
grammable memory elements. Selected memory locations
are permanently changed from their manufactured state, of
all low (VOL) to a logical high (VOH), by the controlled
application of programming potentials and pulses. Careful
adherence to the following programming specifications will
result in high programming yield. Both high VCC (6.0V) and
low VCC (4.0V) verify cycles are specified to assure the
integrity of the programmed fuse. This programming
specification, although complete, does not preclude rapid
programming. The worst case programming time required is
37.4 seconds, and typical programming time can be
approximately 4 seconds per device.
The chip (E) and output enable (G) are used during the
programming procedure. On PROMs which have more than
one output enable control G3 is to be used. The other output
enables must be held in the active, or enabled, state
throughout the entire programming sequence. The program-
mer designer is advised that all pins of the programmer’s
socket should be at ground potential when the PROM is
inserted into the socket. VCC must be applied to the PROM
before any input or output pin is allowed to rise (See Note).
Overall Programming Procedure
1. The address of the first bit to be programmed is
presented, and latched by the chip enable (E) falling
edge. The output is disabled by taking the output enable
G Low: The programming pin is enabled by taking (P)
high.
2. VCC is raised to the programming voltage level, 12.5V.
3. All data output pins are pulled up to VCC program. Then
the data output pin corresponding to the bit to be
programmed is pulled low for 100ms. Only one bit should
be programmed at a time.
4. The data output pin is returned to VCC, and the VCC pin
is returned to 6.0V.
5. The address of the bit is again presented, and latched by
a second chip enable falling edge.
6. The data outputs are enabled, and read, to verify that the
bit was successfully programmed.
a). If verified, the next bit to be programmed is addressed
and programmed.
b). If not verified, the programs verify sequence is
repeated up to 8 times total.
7. After all bits to be programmed have been verified at 6.0V,
the VCC is lowered to 4.0V and all bits are verified.
a). If all bits verify, the device is properly programmed.
b). If any bit fails to verify, the device is rejected.
Programming System Requirements
1. The power supply for the device to be programmed must
be able to be set to three voltages: 4.0V, 6.0V, 12.5V. This
supply must be able to supply 500mA average, and 1A
dynamic, currents to the PROM during programming. The
power supply rise fall times when switching between volt-
ages must be no quicker than 1ms.
2. The address drivers must be able to supply a VIH of 4.0V
and 6.0V and VIL when the system is at programming
voltages. (See Note)
3. The control input buffers must be able to maintain input
voltage levels of ≥ 70% and ≤ 20% VCC for VIH and VIL
levels, respectively. Notice that chip enable (E) and G
does not require a pull up to programming voltage levels.
The program control (P) must switch from ground to VIH
and from VIH to the VCC PGM level. (See Note)
4. The data input buffers must be able to sink up to 3mA
from the PROM’s output pins without rising more than
0.7V above ground, be able to hold the other outputs high
with a current source capability of 0.5mA to 2.0mA, and
not interfere with the reading and verifying of the data
output of the PROM. Notice that a bit to be programmed
is changed from a low state (VOL) to high (VOH) by pulling
low on the output pin. A suggested implementation is
open collector TTL buffers (or inverters) with 4.7kΩ pull
up resistors to VCC. (See Note)
NOTE: Never allow any input or output pin to rise more than 0.3V
above VCC, or fall more than 0.3V below ground.
6-3
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