HIP9022 Ver la hoja de datos (PDF) - Intersil

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componentes Descripción

Fabricante

HIP9022

Dual High Speed Laser Driver

Intersil 

HIP9022

Pin Descriptions (Continued)

PIN

NUMBER

SYMBOL

DESCRIPTION

38

A2

Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.

39

A1

Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.

40

A0

Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.

41

DIAG

Diagnostic output, A 0V - 5V analog signal output limits internally to a range of -0.3V to 5.3V. The output is

the channel addressed by A0 - A3.

42

NC

No connection.

43

TECREFER

External resistor to ground with a resistor value equal to the value of the thermo-resistor at the desired laser

temperature. (Typically in the 5kΩ to 10kΩ range)

44

OT2

Laser out of temperature range indication.

45

TRES2

Thermo-Resistor output to ground connection for TEC control.

46

TECGDR2

Thermo-Electric Cooler Power FET gate drive.

47

TECREF2

Feedback to stabilize the TEC loop.

48

TECFB2

Feedback to stabilize the TEC loop.

49

OC2

Laser over-current indicator flag.

50

LASERON2B Input control turns shunt Power FET gate drive ON/OFF with 5V CMOS logic. Low turns the shunt Power

FET OFF and the Laser ON. These pins have an internal pull-up.

51

CTC2-27K

Thermal compensation long time constant where TTC = External C x 27kΩ. (External C typically equal

0.1µF).

52

CTC2-10K

Thermal compensation short time constant where TTC = External C x 10kΩ. (External C typically equal

0.02µF).

53

XTEN2-

Times 10 constant current monitor amplifier input from the low side of the sense resistor.

54

XTEN2+

Times 10 constant current monitor amplifier input from the high side of the sense resistor.

55

CC2

Gate drive to the current source Power FET.

56

GNDD2

Digital Ground.

57

GNDA2

Analog Ground.

58

VLOW2

Filter capacitor for internally generated shunt Power FET gate lower drive voltage level (1µF).

59

SG_2

Drive output to shunt Power FET gate.

60

VUP2

Filter capacitor for internally generated shunt gate upper voltage level (1µF).

61

V9P

Filter capacitor bypass for internally generated 9V power source (1µF).

62

RLY_OUT

Relay output drive from an N-channel FET controls an external relay to switch the Laser power supply or

power supply interlock ON/OFF for both Laser Drivers.

63

RLY_IN

Relay input control with 5V CMOS logic. A high switches on the relay. This pin has an internal pulldown.

64, 65

ESD LASER PS-2 Laser power supply ESD protection.

66, 67, 68 ESD SHUNT DRAIN-2 Laser diode ESD protection.

4-4

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