6521CBZ Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

6521CBZ

PWM and Triple Linear Power Controller

Intersil 

HIP6521

output voltage. As the internal soft-start voltage increases, the

pulse-width on the PHASE pin increases to reach its

steady-state duty cycle at time T2. At time T3, the 3.3V input

supply starts ramping up; as a result, VOUT2 and VOUT4 start

ramping up on the second attempt (approximately 3.25 SS

cycles wait), at time T4. During the interval between T4 and T5,

the linear controller error amplifiers’ references ramp to the final

value bringing all outputs within regulation limits.

overcurrent event, resulting in an UV condition. Similarly,

after three soft-start periods, the fourth cycle initiates a

ramp-up of this linear output at time T3. One soft-start period

after T3, the linear output is within regulation limits. UV

glitches less than 1µs (typically) in duration are ignored.

VOUT3 (1.8V)

VOUT4 (1.5V)

VOUT1 (2.5V)

+5VSB

+5VDUAL

+3.3VDUAL

+3.3VIN

(0.5V/DIV.)

0V

UV MONITORING

VOUT2 (2.5V)

ACTIVE

0V

(1V/DIV)

VOUT1 (2.5V)

VOUT3 (1.8V)

VOUT2 (2.5V)

VOUT4 (1.5V)

0V

(0.5V/DIV)

T0 T1

T2 T3

T4

T5

TIME

FIGURE 1. SOFT-START INTERVAL

Overcurrent Protection

All outputs are protected against excessive overcurrents.

The PWM controller uses the upper MOSFET’s

on-resistance, rDS(ON) to monitor the current for protection

against shorted output. All linear controllers monitor their

respective FB pins for undervoltage events to protect against

excessive currents.

A sustained overload (undervoltage on linears or overcurrent

on the PWM) on any output results in an independent

shutdown of the respective output, followed by subsequent

individual re-start attempts performed at an interval equivalent

to 3 soft-start intervals. Figure 2 describes the protection

feature. At time T0, an overcurrent event sensed across the

switching regulator’s upper MOSFET (rDS(ON) sensing)

triggers a shutdown of the VOUT1 output. As a result, its

internal soft-start initiates a number of soft-start cycles. After a

three-cycle wait, the fourth soft-start initiates a ramp-up

attempt of the failed output, at time T2, bringing the output in

regulation at time T4.

To exemplify an UV event on one of the linears, at time T1,

the clock regulator (VOUT2) is also subjected to an

6

SOFT-START

FUNCTION

INACTIVE

T0

T1

TIME

T2

T3 T4

FIGURE 2. OVERCURRENT/UNDERVOLTAGE PROTECTION

RESPONSE

As overcurrent protection is performed on the synchronous

switcher regulator on a cycle-by-cycle basis, OC monitoring

is active as long as the regulator is operational. Since the

overcurrent protection on the linear regulators is performed

through undervoltage monitoring at the feedback pins (FB2,

FB3, and FB4), this feature is activated approximately 25%

into the soft-start interval (see Figure 2).

A resistor (ROCSET) programs the overcurrent trip level for

the PWM converter. As shown in Figure 3, the internal

40µA current sink (IOCSET) develops a voltage across

ROCSET (VSET) that is referenced to VIN. The DRIVE

signal enables the overcurrent comparator (OCC). When

the voltage across the upper MOSFET (VDS(ON)) exceeds

VSET , the overcurrent comparator trips to set the

overcurrent latch. Both VSET and VDS(ON) are referenced

to VIN and a small capacitor across ROCSET helps

VOCSET track the variations of VIN due to MOSFET

switching. The overcurrent function will trip at a peak

inductor current (IPEAK) determined by:

IPEAK

=

I--O-----C----S----E----T-----×----R-----O----C-----S----E----T-

rDS(ON)

The OC trip point varies with MOSFET’s rDS(ON)

temperature variations. To avoid overcurrent tripping in the

normal operating load range, determine the ROCSET

resistor from the equation above with:

FN4837.5

October 16, 2006

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