HIP6021 Ver la hoja de datos (PDF) - Intersil

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HIP6021

Advanced PWM and Triple Linear Power Controller

Intersil 

HIP6021

each drive a MOSFET or a NPN bipolar as a pass transistor.

All these transistors should be selected based upon

rDS(ON) , current gain, saturation voltages, gate supply

requirements, and thermal management considerations.

PWM MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes two

loss components; conduction loss and switching loss. These

losses are distributed between the upper and lower

MOSFETs according to duty factor (see the equations

below). The conduction losses are the main component of

power dissipation for the lower MOSFETs. Only the upper

MOSFET has significant switching losses, since the lower

device turns on and off into near zero voltage.

The equations below assume linear voltage-current

transitions and do not model power loss due to the reverse-

recovery of the lower MOSFET’s body diode. The gate-

charge losses are dissipated by the HIP6021 and don't heat

the MOSFETs. However, large gate-charge increases the

switching time, tSW which increases the upper MOSFET

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature at high ambient temperature

by calculating the temperature rise according to package

thermal-resistance specifications. A separate heatsink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

PUPPER

=

I--O-----2----×-----r--D----S----(--O-----N----)---×-----V----O-----U----T-- + I--O------×-----V----I--N-----×-----t--S----W------×-----F----S--

VIN

2

PLOWER

=

I--O-----2----×-----r--D----S----(--O-----N----)---×-----(---V----I--N-----–----V-----O----U----T----)

VIN

+12V

VCC

+5V OR LESS

HIP6021

UGATE

PHASE

-

LGATE

+

PGND

GND

Q1

NOTE:

VGS ≈ VCC -5V

Q2

CR1

NOTE:

VGS ≈ VCC

FIGURE 11. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION

MOSFET body diode from conducting. It is acceptable to

omit the diode and let the body diode of the lower MOSFET

clamp the negative inductor swing, but efficiency could drop

one or two percent as a result. The diode's rated reverse

breakdown voltage must be greater than the maximum input

voltage.

Linear Controller Transistor Selection

The main criteria for selection of transistors for the linear

regulators is package selection for efficient removal of heat.

The power dissipated in a linear regulator is:

PLINEAR = IO × (VIN – VOUT)

Select a package and heatsink that maintains the junction

temperature below the rating with a the maximum expected

ambient temperature.

When selecting bipolar NPN transistors for use with the

linear controllers, insure the current gain at the given

operating VCE is sufficiently large to provide the desired

output load current when the base is fed with the minimum

driver output current.

The rDS(ON) is different for the two equations above even if

the same device is used for both. This is because the gate

drive applied to the upper MOSFET is different than the

lower MOSFET. Figure 11 shows the gate drive where the

upper MOSFET’s gate-to-source voltage is approximately

VCC less the input supply. For +5V main power and +12VDC

for the bias, the gate-to-source voltage of Q1 is 7V. The

lower gate drive voltage is +12VDC. A logic-level MOSFET is

a good choice for Q1 and a logic-level MOSFET can be used

for Q2 if its absolute gate-to-source voltage rating exceeds

the maximum voltage applied to VCC.

Rectifier CR1 is a clamp that catches the negative inductor

swing during the dead time between the turn off of the lower

MOSFET and the turn on of the upper MOSFET. The diode

must be a Schottky type to prevent the lossy parasitic

14

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