HIP6021 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

HIP6021

Advanced PWM and Triple Linear Power Controller

Intersil 

HIP6021

+5VIN

LIN

CIN

+3.3VIN

+12V

CVCC

VCC GND

OCSET1

Q3

VOUT2

DRIVE2

UGATE1

COUT2

PHASE1

VOUT3

LGATE1

SS

CSS

HIP6021

COCSET1

ROCSET1

Q1

LOUT1

VOUT1

COUT1

CR1

Q2

VOUT4

COUT3

Q4

DRIVE3 DRIVE4

PGND

COUT4

Q5

+3.3VIN

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 8. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

OSC

∆VOSC

PWM

COMP

-

+

VIN

DRIVER

LO

DRIVER

PHASE CO

VOUT

ZFB

VE/A

-

+

ZIN

ERROR REFERENCE

AMP

ESR

(PARASITIC)

DETAILED COMPENSATION COMPONENTS

C2

C1 R2

ZFB

VOUT

ZIN

C3 R3

R1

COMP

FB

-

+

HIP6021

DACOUT

FIGURE 9. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Compensation Break Frequency Equations

FZ1

=

-----------------1------------------

2π × R2 × C1

FZ2 = 2----π-----×-----(--R-----1-----+-1----R-----3---)----×-----C-----3-

FP1

=

---------------------------1---------------------------

2

π

×

R2

×





C-C----11-----+×-----CC-----22--

FP2 = 2----π-----×-----R---1--3-----×----C-----3--

Figure 10 shows an asymptotic plot of the DC-DC

converter’s gain vs. frequency. The actual Modulator Gain

has a high gain peak dependent on the quality factor (Q) of

the output filter, which is not shown in Figure 9. Using the

above guidelines should yield a Compensation Gain similar

to the curve plotted. The open loop error amplifier gain

bounds the compensation gain. Check the compensation

gain at FP2 with the capabilities of the error amplifier. The

Closed Loop Gain is constructed on the log-log graph of

Figure 10 by adding the Modulator Gain (in dB) to the

Compensation Gain (in dB). This is equivalent to multiplying

the modulator transfer function to the compensation transfer

function and plotting the gain.

The compensation gain uses external impedance networks

ZFB and ZIN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

FZ1

FZ2 FP1 FP2

OPEN LOOP

100

ERROR AMP GAIN

80

20

log







V-V----P-I--N-P---

60

40

COMPENSATION

GAIN

20

0

-20

20

log





RR-----21--

MODULATOR

-40

GAIN

FLC FESR

-60

10

100

1K

10K 100K

FREQUENCY (Hz)

CLOSED LOOP

GAIN

1M 10M

FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

Component Selection Guidelines

Output Capacitor Selection

The output capacitors for each output have unique

requirements. In general, the output capacitors should be

selected to meet the dynamic regulation requirements.

Additionally, the PWM converters require an output capacitor

to filter the current ripple. The load transient for the

microprocessor core requires high quality capacitors to

supply the high slew rate (di/dt) current demands.

12

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