HIP0063 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

Fabricante

HIP0063

Hex Low Side MOSFET Driver with Serial or Parallel Interface and Diagnostic Fault Control

Intersil 

Specifications HIP0063

Serial Peripheral Interface Timing (See Figure 4)

PARAMETERS

SYMBOL

TEST CONDITION

Clock Operating Frequency

Clock Period

Clock High Time

Clock Low Time

Falling Edge of CS to Rising Edge of SCK

Falling Edge of SCK to Rising Edge of CS

SI to SCK Setup Time

SI Hold After SCK Rise

Rise Time of Incoming Signals

Fall Time of Incoming Signals

SO Data Valid to Falling Edge of SCK

Falling Edge of SCK to SO

Rise Time of SO

Fall Time of SO

Falling Edge of CS to SO Operational

(1kΩ Pulldown on SO Pin)

fSCK

tSCK

tWH

tWL

tLEAD

tLAG

tSU2

tH2

trSI

tfSI

tSU1

tH1

trSO

tfSO

tSOEN

CL = 200pF

SCK = 0.8V to 0.8V

SCK = 2V TO 2V; fSCK = 1.8MHz

SCK = 0.8V TO 0.8V; fSCK = 1.8MHz

CS = 0.8V to SCK = 2V

SCK = 0.8V to CS = 2V

SI = 0.8, 2V to SCK = 2V;

fSCK = 2.25MHz

SCK = 2V to SI Hold

CL = 200pF

CL = 200pF

SO = 0.8, 2V to SCK = 0.8V; CL = 200pF

SO = 0.8, 2V to SCK = 0.8V; CL = 200pF

CL = 200pF

CL = 200pF

CS = 0.8V to SO Low Impedance

Rising Edge of CS to SO Three-State

(1kΩ Pulldown on SO Pin)

tSODIS CS = 2V to SO Three-State

Rising Edge of SCK to SO (Data Valid)

tVALID CL = 200pF, 1.8MHz

CL = 200pF, 2.25MHz

MIN TYP MAX UNITS

1.8

4

- MHz

-

250 555 ns

-

100 248 ns

-

100 248 ns

-

150 200 ns

-

50 200 ns

-

25 55 ns

-

10 55 ns

-

-

120 ns

-

-

120 ns

80

-

-

ns

80 125

-

ns

-

30 50 ns

-

30 50 ns

-

150 300 ns

-

150 200 ns

-

-

172 ns

-

-

117 ns

CS

SCK

SI

SO

tSCK

tLEAD

1

2

tWL

tVALID

(MSB = 0)

tSU2

tWH

X

tH2

LSB

tLAG

tSODIS

LAST BIT

XMITTED

MSB

tSOEN

tSU1

tH1

LSB

FIGURE 4. TIMING DIAGRAM FOR THE HIP0063 SHOWING THE SPI BUS INPUT CONTROL SIGNALS

5

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