HI1179 Ver la hoja de datos (PDF) - Intersil

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Fabricante

HI1179

8-Bit, 35 MSPS, Video A/D Converter

Intersil 

HI1179

function is enabled by tying CLE low. In this case a negative

going pulse is sent to the CLP pin. VIN will now be clamped

during the low period of the clamp pulse to the voltage on

the VREF pin. Figure 15 shows the HI1179 configured for

this mode of operation.The clamp pulse is latched by the

ADC sampling clock through an external latch. This is not

necessary to the operation of the clamp function but in video

applications, if this is not done, then a slight beat might be

generated as vertical sag according to the relation between

the sampling frequency and the clamp frequency. The pulse

width of the input clamp pulse will depend on the input

signal. For example, a 1µs pulse width will allow the user to

clamp the back porch of an NTSC input signal to the

reference voltage, VREF.

The clamp can be disabled by tying CLE high and then the

HI1179 acts like a normal A/D converter, accepting a DC

coupled input. The Typical Application Schematic illustrates

the operation of HI1179 when the clamp function is not used.

Additional information on the HI1179 is available in

Application Note 9407, “Using the HI1176/HI1179 Evaluation

Board”.

Test Circuits

+V

S2

-

S1: ON IF A < B

+

S1

S2: ON IF A > B

-V

A<B A>B

COMPARATOR

VIN

DUT

8

A8

B8

8

HI1179

DVM

A1

A0

“0”

CLK (35MHz)

B1

B0

“1”

CONTROLLER

BUFFER

000 • • • 00

8

TO

111 • • • 10

FIGURE 23. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT

2.6V

fC -1kHz

SG

0.6V

1

AMP

2

VIN DUT

HI1179

NTSC

SIGNAL

40 IRE

SOURCE 100 MODULATION

2.6V

IRE

0

- 40

BURST

SYNC

0.6V

SG

(CW) fC

8 TTL

ECL

TTL

ECL

HI20201

1

8

10-BIT

D/A

2

CLK

620

-5.2V

620

-5.2V

ERROR RATE

HPF

COUNTER

VECTOR

SCOPE

DG

DP

FIGURE 24. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT

4-1120

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