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HI-8282A Datasheet PDF : 15 Pages
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HI-8282A
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-8282A contains 10 data flip flops whose D inputs are con-
nected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
DATA
BUS FUNCTION CONTROL
PIN
DESCRIPTION
BDO5
If enabled, an internal connection
SELF TEST 0 = ENABLE is made passing 429DO and
429DO to the receiver logic inputs
RECEIVER 1
BDO6 DECODER 1 = ENABLE
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO7
-
If Receiver 1 Decoder is
-
enabled, the ARINC bit 9
must match this bit
BDO8
-
If Receiver 1 Decoder is
-
enabled, the ARINC bit 10
must match this bit
RECEIVER 2
BDO9 DECODER 1 = ENABLE
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
BD10
-
If Receiver 2 Decoder is
-
enabled, then ARINC bit 9
must match this bit
BD11
-
If Receiver 2 Decoder is
-
enabled, then ARINC bit 10
must match this bit
BD12
INVERT
XMTR
PARITY
Logic 0 enables normal odd parity
1 = ENABLE and Logic 1 enables even parity
output in transmitter 32nd bit
BD13 XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
BD14 RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
429DI1(A)
OR
429DI2(A)
429DI1(B)
OR
429DI2(B)
vcc
GND
vcc
DIFFERENTIAL
AMPLIFIERS
COMPARATORS
ONES
NULL
ZEROES
GND
FIGURE 1. ARINC RECEIVER INPUT
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with the
receiver or transmitter. ARINC bit 1 is the first bit transmitted or
received.
BYTE 1
DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8
BIT
DATA
BUS
ARINC
BIT
BYTE 2
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-8282A guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13v signal level).
Design tolerances guarantee detection of the above levels, so the
actual acceptance ranges are slightly larger. If the ARINC signal is
out of the actual acceptance ranges, including the nulls, the chip
rejects the data.
HI-8282A-10
The HI-8282A-10 option is similar to the HI-8282A with the exception
that it allows an external 10K to 15K ohm resistor to be added in
series with each ARINC input without affecting the ARINC input
thresholds. This option is especially useful in applications where
lightning protection circuitry is also required.
Each side of the ARINC bus must be connected through a 10K to 15K
ohm series resistor in order for the chip to detect the correct ARINC
levels. The typical 10 volt differential signal is translated and input to
a window comparator and latch. The comparator levels are set so
that with the external 10K to 15K ohm resistors, they are just below
the standard 6.5 V minimum ARINC data threshold and just above
the 2.5 V maximum ARINC null threshold.
The receivers of the HI-8282A-10, when used with external
15K ohm resistors, will withstand DO-160F, Level 3, waveforms 3,
4, 5A and 5B pin injection. No additional lightning protection circuit
is necessary.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
HOLT INTEGRATED CIRCUITS
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