HFBR-0508Z Ver la hoja de datos (PDF) - Avago Technologies
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componentes Descripción
Fabricante
HFBR-0508Z
Avago Technologies
HFBR-0508Z Datasheet PDF : 8 Pages
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HFBR-2528Z Receiver
The HFBR-2528Z receiver consists
of a silicon PIN photodiode and
digitizing IC to produce a logic
compatible output. The IC
includes a unique circuit to
correct the pulse width distortion
of the first bit after a long idle
period. This enables operation
from DC to 10 MBd with low PWD
for arbitrary data patterns.
The receiver output is a “push-
pull” stage compatible with TTL
and CMOS logic. The receiver
housing is a dark, conductive
plastic, compatible with all
Versatile Link connectors.
GROUND 5
GROUND 8
4 NO CONNECT
3 VCC
IC
2 GROUND
1 VO
SEE NOTES 5,7
HFBR-2528Z Receiver, top view
Electrical and Optical Characteristics: TA = -40° to +85°C, 4.75 V < VCC < 5.25 V, unless otherwise noted.
Parameter
Symbol Min. Typ.[1] Max. Unit
TA (°C)
Condition
Note Fig.
Peak POF Sensitivity:
Minimum Input for
Logic “0”
PRL,min
-23.0 -21.0 dBm
+25 1 mm POF,
2,6 2,4
-20.0
0 to +70 |PWD| < 30 ns
-19.5
-40 to +85
Peak POF Overdrive
Limit:Maximum
Input for Logic “0”
PRL,max +1.0 +5.0
+0.0
-1.0
dBm
+25 1 mm POF,
0 to +70 |PWD| < 30 ns
-40 to +85
2,3, 1,2,
6
3
Peak POF Off State
Limit: Maximum
Input for Logic “1”
PRH,max
-42 dBm
1 mm POF
2,6,
8
Peak HCS
Sensitivity: Minimum
Input for Logic “0”
PRL,min
-25.0 -23.0 dBm
+25
200 µm HCS,
2,6
-22.0
0 to +70 |PWD| < 30 ns
-21.5
-40 to +85
Peak HCS Overdrive
Limit: Maximum
Input for Logic “0”
PRL,max -1.0 +3.0
-2.0
-3.0
dBm
+25
200 µm HCS,
2,3,
0 to +70 |PWD| < 30 ns 6
-40 to +85
Peak HCS Off State
Limit: Maximum
Input for Logic “1”
PRH,max
-44 dBm
200 µm HCS
2,6,
8
Supply Current
High Level Output
Voltage
ICC
27 45 mA
VOH
4.2 4.7
V
VO = Open
IO = -40 µA
Low Level Output
VOL
Voltage
0.22 0.4
V
IO = +1.6 mA
Output Rise Time
tr
Output Fall Time
tf
Thermal Resistance,
θjc
Junction to Case
12 30
ns
10 30
ns
200
°C/W
CL = 10 pF
6
CL = 10 pF
6
4
Electric Field
Immunity
EMAX
8
V/m
Near Field,
5
Electrical
Field Source
Power Supply
PSNI 0.1 0.4
V
pp
Noise Immunity
Sine Wave
6
DC - 10 MHz
Notes:
1. Typical data are at +25°C, VCC = 5.0 V.
2. Input power levels are for peak (not average) optical input levels. For 50% duty cycle data, peak optical power is twice the average optical power.
3. Receiver overdrive (PRL,max) is specified as the limit where |PWD| will not exceed 30 ns. The receiver will be in the correct state (logic “0”) for
optical powers above PRL,max. However, it may not meet a 30% symbol period PWD if the overdrive limit is exceeded. Refer to Figure 2 for PWD
performance at high received optical powers.
4. Typical value measured from junction to PC board solder joint for horizontal mount package, HFBR-2528Z.
5. Pins 5 and 8 are electrically connected to the conductive housing and are also used for mounting and retaining purposes. It is required that pins 5
and 8 be connected to ground to maintain conductive housing shield effectiveness.
6. In recommended receiver circuit, with an optical signal from the recommended transmitter circuit.
7. Pin 4 is electrically isolated internally. Pin 4 may be externally connected to pin 1 for board layout compatibility with HFBR-25X1Z, HFBR-25X2Z and
HFBR-25X4Z. Otherwise it is recommended pin 4 be grounded as in Figure 5.
8. BER ≤ 10E-9, includes a 10.8 dB margin below the receiver switching threshold level (signal to noise ratio = 12).
5
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