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HEF4518

Dual BCD counter

Philips Electronics 

Philips Semiconductors

Dual BCD counter

Product specification

HEF4518B

MSI

DESCRIPTION

T he HEF4518B is a dual 4-bit internally synchronous BCD

counter. The counter has an active HIGH clock input

(CP0) and an active LOW clock input (CP1), buffered

outputs from all four bit positions (O0 to O3) and an active

HIGH overriding asynchronous master reset input (MR).

The counter advances on either the LOW to HIGH

transition of the CP0 input if CP1 is HIGH or the HIGH to

LOW transition of the CP1 input if CP0 is LOW. Either CP0

or CP1 may be used as the clock input to the counter and

the other clock input may be used as a clock enable input.

A HIGH on MR resets the counter (O0 to O3 = LOW)

independent of CP0, CP1.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

Fig.1 Functional diagram.

PINNING

CP0A, CP0B

CP1A, CP1B

MRA, MRB

O0A to O3A

O0B to O3B

clock inputs (L to H triggered)

clock inputs (H to L triggered)

master reset inputs

outputs

outputs

Fig.2 Pinning diagram.

HEF4518BP(N): 16-lead DIL; plastic (SOT38-1)

HEF4518BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)

HEF4518BT(D): 16-lead SO; plastic (SOT109-1)

( ): Package Designator North America

APPLICATION INFORMATION

Some examples of applications for the HEF4518B are:

• Multistage synchronous counting.

• Multistage asynchronous counting.

• Frequency dividers.

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

2

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