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HEF4505B

64-bit, 1-bit per word random access read/write memory

Philips Electronics 

Philips Semiconductors

64-bit, 1-bit per word random access

read/write memory

Product specification

HEF4505B

LSI

Figure 5 shows a 256-word by n-bit static RAM system.

The outputs of the four HEF4505B circuits are tied

together to form 256 words by 1-bit. Additional bits are

attained by paralleling the inputs in groups of four.

Memories of larger words can be attained by decoding the

most significant bits of the address and AND-ing them with

the strobe input.

Fan-in and fan-out of the memory are limited only by speed

requirements. The extremely low input and output leakage

currents keep the output voltage levels from changing

significantly as more outputs are tied together. With the

output levels independent of fan-out, most of the power

supply range is available as logic swing, regardless of the

number of units wired together. As a result, high noise

immunity is maintained under all conditions.

The memory system shown in Fig.5 can be interfaced

directly with other ICs of the LOCMOS HE family. No

external components are required.

Non-volatile information storage is allowed due to very low

power dissipation when the memory is powered by a small

standby battery. Figure 6 shows an optional standby

power supply circuit for making a LOCMOS memory

‘non-volatile’. When the usual power fails, a battery is used

to sustain operation or maintain stored information. While

normal power supply voltage is present, the battery is

trickle-charged through a resistor (R) which sets the

charging rate. In Fig.6 the sustaining voltage is VB, and + V

is the ordinary voltage from a power supply. VDD is

connected to the power supply pin of the memory.

Low-leakage diodes are recommended to conserve

battery power.

Fig.6 Standby battery circuit.

January 1995

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