HEF4027B Ver la hoja de datos (PDF) - NXP Semiconductors.
Número de pieza
componentes Descripción
Fabricante
HEF4027B Datasheet PDF : 14 Pages
| |||
NXP Semiconductors
HEF4027B
Dual JK flip-flop
Table 7. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Extrapolation formula[1] Min Typ Max Unit
fmax
maximum
frequency
CP input;
J = K = HIGH;
see Figure 5
5V
10 V
15 V
4
8
-
12 25 -
15 30 -
MHz
MHz
MHz
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] tt is the same as tTLH and tTHL.
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD
Typical formula for PD (W)
Where:
PD
dynamic power 5 V
PD = 900 fi + (fo CL) VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 4500 fi + (fo CL) VDD2
fo = output frequency in MHz;
15 V
PD = 13200 fi + (fo CL) VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
(fo CL) = sum of the outputs.
12. Waveforms
tr
tf
VI
SD, CD or CP
INPUT
0V
10 %
90 %
VM
tPLH
VOH
Q or Q
OUTPUT
VOL
VM
10 %
90 %
tTLH
tPHL
tTHL
001aah863
Fig 4.
VOH and VOL are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9.
Waveforms showing rise, fall and transition times and propagation delays
CP INPUT
1/fmax
tW
VM
th
J,K INPUT
VM
tsu
001aae596
Measurement points are given in Table 9.
Fig 5. Waveforms showing set-up and hold times and minimum clock pulse width
HEF4027B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
7 of 14
Share Link: 