HDMP-0482 Ver la hoja de datos (PDF) - HP => Agilent Technologies

Número de pieza

componentes Descripción

Fabricante

HDMP-0482

Octal Cell Port Bypass Circuit with CDR and Data Valid Detection

HP => Agilent Technologies 

Figure 5. Eye Diagram of TO_NODE[1]± High Speed Differential Output.

Note: Measurement taken with a 27-1 PRBS input to FM_NODE[0]±.

HP70841B

+/- Data

Pattern Generator

K28.7

Clock

2

HDMP-0482

+/- FM_NODE[0]

BYPASS[0]-

N/C

BYPASS[1:4]-

Bias Tee

1 KΩ

REFCLK

+/- TO_NODE[0]

1062.5 MHz

1.4V

106.25 MHz

2

HP 70311A

Clock Source

1/10

106.25 MHz

Trigger

Ch 1/2

HP 83480A

Digital

Communication

Analyzer

Figure 6. Setup for Measurement of Random Jitter.

HP70841B

+/- Data

Pattern Generator

+K28.5 -K28.5

Clock

2

HDMP-0482

+/- FM_NODE[0]

BYPASS[0]-

N/C

BYPASS[1:4]-

Bias Tee

1 KΩ

REFCLK

+/- TO_NODE[0]

1062.5 MHz

1.4V

106.25 MHz

2

HP 70311A

Clock Source

1/10

106.25 MHz

Ch 1/2

HP 83480A

1/10

Trigger

53.125 MHz

Digital

Communication

Analyzer

Figure 7. Setup for Measurement of Deterministic Jitter.

9

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