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HDMP-1687

Four Channel SerDes Circuit for Gigabit Ethernet and Fibre Channel

HP => Agilent Technologies 

• TTL parallel I/Os

• High-speed phase locked loops

• Parallel-to-serial converter

• High-speed serial clock and

data recovery circuitry

• Comma character recognition

circuitry for 8B/10B

• Character alignment circuitry

• Serial-to-parallel converter

PARALLEL INPUT LATCH

The transmitter accepts 10-bit

wide single-ended TTL parallel

data at inputs TX [0:3] [0:9]. The

RFCT pin is used as transmit byte

clock. The TX [0:3] [0:9] and

RFCT signals must be properly

aligned, as shown in Figure 3.

RFCT is also used as a clean fre-

quency reference for the receiver

PLLs.

TX PLL/CLOCK GENERATOR

The transmitter Phase Locked

Loop and Clock Generator (TX

PLL/CLOCK GENERATOR) block

generates all internal clocks

needed by the transmitter section

to perform its functions. These

clocks are based on the supplied

reference clock (RFCT). RFCT is

used as the frequency reference

clock for the PLL as well as for

the incoming data latches. The

RFCT clock is multiplied by 10 to

generate the serial rate clock

necessary for clocking the high

speed serial outputs.

FRAME MUX

The FRAME MUX accepts the

10-bit wide parallel data from the

INPUT LATCH. Using internally

generated high speed clocks, this

parallel data is multiplexed into

serial data streams. The data bits

are transmitted sequentially, from

TX [0:3] [0] to TX [0:3] [9].

SERIAL OUTPUT SELECT

The OUTPUT SELECT block

provides for an optional internal

loopback of the high speed serial

signal for testing purposes.

In normal operation, LOOP is set

low and the serial data stream is

placed at SO [0:3] ± . When

wrap-mode is activated by setting

LOOP high, the SO [0:3] ± pins

are held static at logic 1 and the

serial output signal is internally

wrapped to the INPUT SELECT

block of the receiver section.

SERIAL INPUT SELECT

The INPUT SELECT block deter-

mines whether the signal at

SI [0:3]± or the internal loop-

back serial signal is used. In

normal operation, LOOP is set

low and the serial data is ac-

cepted at SI [0:3] ± . When LOOP

is set high, the outgoing high

speed serial signal is internally

looped-back from the transmitter

section to the receiver section.

This feature allows parallel

loopback testing, exclusive of the

transmission medium.

RX PLL/CLOCK RECOVERY

The RX PLL/CLOCK RECOVERY

block is responsible for frequency

and phase locking onto the in-

coming serial data stream and

recovering the bit and byte

clocks. The Rx PLL continually

frequency locks onto the refer-

ence clock, and then phase locks

onto the selected input data

stream. The frequency lock part

of the PLL is shared among all

channels. Phase locking is per-

formed separately on each chan-

nel. An internal signal detection

circuit monitors the presence of

the input, and invokes the phase

detection once the minimum

differential input signal level is

supplied (AC Electrical Specifica-

tions). Once bit locked, the re-

ceiver generates the high speed

sampling clock at serial data

rates for the input sampler.

SERIAL INPUT SAMPLER

The INPUT SAMPLER converts

the serial input signal into a high

speed serial bit stream. In order

to accomplish this, it uses the

high speed serial clock recovered

from the RX PLL/CLOCK RECOV-

ERY block. This serial bit stream

is sent to the FRAME DEMUX

AND BYTE SYNC block.

FRAME DEMUX, BYTE SYNC

The FRAME DEMUX, BYTE

SYNC block is responsible for

restoring the 10-bit parallel data

from the high speed serial bit

stream. This block is also re-

sponsible for recognizing the

comma character (K28.5+) of

positive disparity (0011111xxx).

When recognized, the FRAME

DEMUX, CHAR SYNC block

works with the RX PLL/CLOCK

RECOVERY block to properly

select the parallel data edge out

of the bit stream so that the

comma character starts at bit

RX [0:3] [0]. When a comma

character is detected and realign-

ment of the receiver byte clock

RC [0:3] [0:1] is necessary, this

clock is stretched, not slivered, to

the next possible correct align-

ment position. This clock will be

fully aligned by the start of the

second 4-byte ordered set. The

second comma character received

will be aligned with the rising

edge of RC [0:3] [1] and will

follow it with a delay. This delay

guarantees hold time at the re-

ceiving ICs input latches. Comma

characters of positive disparity

must not be transmitted in con-

secutive bytes to allow the re-

ceiver byte clocks to maintain

their proper recovered frequen-

cies.

PARALLEL OUTPUT DRIVERS

The OUTPUT DRIVERS present

the 10-bit parallel recovered data

byte properly aligned to the

receive byte clocks RC [0:3]

[0:1] as shown in Figure 5.

These output data buffers provide

single ended TTL compatible

signals.

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