HDD128M72D18RPW Ver la hoja de datos (PDF) - Hanbit Electronics Co.,Ltd

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HDD128M72D18RPW

DDR SDRAM Module 1024Mbyte (128Mx72bit), based on 64Mx8, 4Banks, 8K Ref., 184Pin-DIMM with PLL & Register

Hanbit Electronics Co.,Ltd 

HANBit

HDD128M72D18RPW

PIN FUNCTION DESCRIPTION

Pin

Name

Input Function

CK and /CK are differential clock inputs. All address and control input signals are sampled

CK, /CK

Clock

on the positive edge of CK and negative edge of /CK. Output (read) data is referenced to

both edges of CK. Internal clock signals are derived from CK/ /CK.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input

buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN

and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in

CKE

Clock Enable

any bank). CKE is synchronous for all functions except for disabling outputs, which is

achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during

power-down and self refresh modes, providing low standby power. CKE will recognizean

LVCMOS LOW level prior to VREF being stable on power-up.

CS enables(registered LOW) and disables(registered HIGH) the command decoder.

/CS0, /CS1

Chip Select

All commands are masked when CS is registered HIGH. CS provides for external bank

selection on systems with multiple banks. CS is considered part of the command code.

A0 ~ A12

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11

BA0 ~ BA1

Bank select address

BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command

is being applied.

/RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row

access & precharge.

/CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with /CAS low. Enables

column access.

/WE

Write enable

Enables write operation and row precharge.

Latches data in starting from /CAS, /WE active.

DQS0 ~ 7

Data Strobe

Output with read data, input with write data. Edge-aligned with read data, cen-tered in write

data. Used to capture write data.

DM0~7

Input Data Mask

DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH

along with that input data during a WRITE access. DM is sampled on both edges of DQS.

DM pins include dummy loading internally, to matches the DQ and DQS load-ing.

DQ0 ~ 63

Data input/output

Data inputs/outputs are multiplexed on the same pins.

VDDQ

VDD

VSS

VREF

Supply

Supply

Supply

Supply

DQ Power Supply : +2.5V ± 0.2V.

Power Supply : +2.5V ± 0.2V (device specific).

DQ Ground.

SSTL_2 reference voltage.

VSPD

Supply

Serial EEPROM Power Supply : 3.3v

VDDID

VDD identification Flag

URL : www.hbe.co.kr

REV 1.0 (January. 2005)

4

HANBit Electronics Co.,Ltd.

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